Just-in-time FPGA Hardware Compilation via Distributed Simulation
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Solution Overview
Problem
The increasing transistor density in semiconductor devices leads to excessive power consumption, exceeding safe thermal limits and limiting clock speed and computing performance, while current FPGA design processes are lengthy and inefficient, hindering the adoption and optimization of FPGA designs.
Innovation Solution
A method that involves a distributed hardware system where a hardware design in a hardware description language is compiled and simulated across multiple software and hardware engines, allowing for just-in-time hardware creation and efficient execution on FPGAs, enabling design flexibility and optimization across different FPGA types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor density is increased to improve computing performance, then the number of transistors available on a semiconductor device increases, but power consumption exceeds safe thermal limits
Solution Approach 1:
The system segments the hardware design into reusable components that can be independently compiled and executed on different FPGA devices. This allows the computing workload to be distributed across multiple devices, enabling parallel processing that improves overall computing performance without requiring excessive power consumption from a single high-density device.
Solution Approach 2:
The patent creates a universal component library that can be executed on various FPGA devices from different vendors. This multi-functionality allows the same hardware design to run on devices with different power characteristics, enabling optimization for power efficiency while maintaining computing performance through device selection and configuration.
2Manufacturing precision
If traditional FPGA design process is used to achieve optimized hardware design, then design can be targeted to specific FPGA type, but design cycle becomes extremely lengthy
Solution Approach 1:
The system performs preliminary compilation of hardware components into an intermediate representation that can be quickly deployed to different FPGA devices. By pre-compiling components and creating a vendor-agnostic intermediate format, the design process eliminates lengthy re-compilation steps when targeting different devices, significantly reducing the design cycle while maintaining optimization capabilities.
Solution Approach 2:
The patent creates copies of hardware components in an intermediate representation format that can be instantiated on different FPGA devices without requiring full re-compilation. This copying approach allows rapid deployment and testing of hardware designs across multiple device types, reducing the iterative design cycle time while preserving design optimization.
3Productivity
If hardware design is compiled to specific FPGA type to achieve optimal performance, then performance is maximized, but adaptability to different FPGA vendors is lost
Solution Approach 1:
The patent introduces an intermediate representation layer between the hardware component library and the target FPGA devices. This intermediary format preserves the optimized performance characteristics of the original design while enabling translation to multiple vendor-specific FPGA architectures. The intermediate representation acts as a mediator that maintains performance fidelity while providing vendor adaptability.
Data Source
AI summary
A method for implementing a distributed hardware system includes retrieving a hardware design described in a hardware description language, where the hardware design includes a plurality of components. The method further includes, for each component of the hardware design, sending the component to a hardware compiler and to one of a plurality of software engines, where the hardware compiler compiles the component to run in one of a plurality of hardware engines and the one software engine simulates the component while the hardware compiler compiles the component for the one hardware engine, and upon completion of the compilation of the component, sending the compiled component to one of the hardware engines to be executed by the one hardware engine and monitoring communication so that the one hardware engine can interact with other components in other hardware engines or software engines.