Jitter-Impedance Delay Lock Loop for Precise Clock Alignment
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Solution Overview
Problem
Existing memory devices face issues with clock signal jitter due to coarse adjustments in delay lock loops, leading to misalignment with data strobe signals and increased latency.
Innovation Solution
Implementing a control component in the DLL circuit to restrict delay adjustments within a threshold, allowing for fine adjustments and reducing jitter, thereby aligning the clock signal with the data strobe signal more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If coarse adjustments are made in the DLL circuit, then the delay can be changed in larger increments, but the clock signal jitter increases and misalignment with data strobe signals occurs
Solution Approach 1:
The delay adjustment is segmented into two independent components: a coarse delay adjustment unit that provides large-step delay changes for rapid alignment, and a fine delay adjustment unit that provides small-step delay changes for precise alignment. This segmentation allows the system to achieve both fast convergence and high precision without the limitations of using only coarse adjustments.
2Measurement precision
If the DLL circuit loops multiple times to adjust delay, then the alignment can be refined, but the latency increases
Solution Approach 1:
The coarse delay adjustment unit performs preliminary alignment by rapidly adjusting the delay through large increments based on the initial phase difference detection. This preliminary action brings the clock signal close to alignment without requiring multiple loop iterations, thereby reducing the overall adjustment latency while maintaining the ability to achieve precise alignment through subsequent fine adjustments.
Data Source
AI summary
Methods, systems, and devices for a jitter impedance delay lock loop are described. A delay lock loop circuit may be configured to align a clock signal and a data strobe signal. The delay lock loop circuit may include a variable delay component configured to receive the clock signal and output an aligned clock signal. The delay lock loop circuit may include a phase detector configured to determine whether the clock signal is aligned with the data strobe signal and output an indication to increase or decrease a delay to the clock signal. The variable delay component may increase or decrease the delay based on the indication from the phase detector. The delay lock loop circuit may include a control component configured to restrict the increase or decrease of the delay such that the delay does not exceed a threshold.