Jog Design in Gate Strips for Isolation and Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Metal-Oxide-Semiconductor (MOS) devices with Shallow Trench Isolation (STI) regions require more chip area, leading to reduced device density due to the need for larger gate electrode strips for device isolation.
Innovation Solution
The introduction of a jog design in gate strips that overlap the active region and STI regions, allowing for a continuous gate electrode and dielectric structure, which increases the landing area for contact plugs and reduces contact resistance by aligning the jog with the active region, thereby enhancing the process window for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Shallow Trench Isolation (STI) regions are used for device isolation, then device isolation is achieved, but chip area increases and device density decreases
Solution Approach 1:
The gate strip is extended into a third dimension by adding a jog portion that overlaps the active region. This dimensional extension allows the gate strip to provide isolation function previously requiring separate STI structures, thereby reducing the area occupied by STI regions while maintaining device isolation reliability.
Solution Approach 2:
The gate strip is designed to perform multiple functions: it serves as both the gate electrode for device operation and as an isolation structure by extending into the STI region. This multi-functionality eliminates the need for separate dedicated isolation structures, reducing overall chip area while maintaining isolation effectiveness.
2Reliability
If gate electrode strip is extended for device isolation, then isolation is improved, but device density is reduced
Solution Approach 1:
Instead of extending the gate strip horizontally which would consume more chip area and reduce device density, the invention extends it vertically by overlapping the active region. This dimensional change allows the same gate strip to provide isolation functionality without increasing the horizontal footprint, thereby maintaining high device density.
3Reliability
If jog design is introduced in gate strip, then landing area for contact plugs increases and contact resistance decreases, but gate strip structure becomes more complex
Solution Approach 1:
The gate strip is segmented into a main body portion and a jog portion that overlaps the active region. This segmentation allows the jog portion to specifically provide the landing area for contact plugs, improving electrical connectivity, while the main body portion maintains the standard gate strip structure, balancing functionality with manufacturing simplicity.
Data Source
AI summary
A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.