JTAG Clock Synchronization via Composite Return Signal
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Solution Overview
Problem
In processing systems with multiple modules operating at different clock rates, timing errors occur due to inconsistencies between system clock and return clock signals, leading to compromised test and debug procedures, especially when not all modules are subjected to a particular test, which can reduce the speed and accuracy of the process.
Innovation Solution
A selection unit generates synchronized return clock positive edge (RCLK_PE) and negative edge (RCLK_NE) signals for selected modules, combining them into a composite RCLK signal, while continuously applying these signals to non-selected modules to ensure seamless transitions and identify timing issues by comparing the composite RCLK with the system clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all modules are included in the test procedure, then test coverage is improved, but test speed and accuracy deteriorate due to timing errors from clock rate variations
Solution Approach 1:
The system segments the module set into selected and non-selected groups using selection units. Each module has an individual selection unit that determines whether its RCLK signal contributes to the composite RCLK. This segmentation allows the test procedure to focus only on selected modules, improving test speed while maintaining adequate coverage through selective testing.
Solution Approach 2:
The system dynamically adjusts module participation in the test procedure through selectable modules. The selection units enable or disable individual module contributions to the composite RCLK signal based on test requirements. This dynamic configuration allows optimization of test speed by excluding non-critical modules while maintaining test coverage for critical modules.
2Adaptability or versatility
If modules operate at different clock rates, then module functionality is improved, but timing synchronization deteriorates causing timing errors
Solution Approach 1:
The composite RCLK signal serves as an intermediary that mediates between modules operating at different clock rates. The combiner circuit generates this composite signal by selectively combining RCLK signals from individual modules through selection units. This intermediary allows modules to operate independently at their optimal clock rates while maintaining synchronization for selected modules through the unified composite RCLK.
Solution Approach 2:
The system segments the clock synchronization problem by allowing individual modules to maintain their own clock rates while using selection units to control which modules contribute to the composite RCLK. This segmentation enables each module to operate at its optimal speed while selected modules are synchronized through their contribution to the composite signal.
3Productivity
If non-selected modules are excluded from test procedure, then test speed is improved, but timing error detection capability deteriorates
Solution Approach 1:
The system applies partial action by including only selected modules in the composite RCLK generation rather than all modules. The selection units enable or disable individual module contributions based on test priorities. This partial inclusion improves test speed by focusing resources on critical modules while maintaining adequate timing error detection capability for the selected subset.
Data Source
AI summary
In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit.