JTAG TMS/TCK Serial Bus for Low-Latency TAP Communication
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Solution Overview
Problem
The IEEE 1149.1 TAP interface, used for test, debug, and programming operations in ICs and cores, suffers from data latency and limited bandwidth due to serial traversal of multiple TAP domains, which restricts communication efficiency.
Innovation Solution
Utilizing the TMS and TCK connections as a direct serial bus between ICs, cores, and controllers, allowing data to be transmitted directly without affecting the steady-state operation of TAP domains, thereby bypassing intermediate domains and enhancing communication bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is transmitted through multiple TAP domains in series, then all TAP domains can be accessed uniformly, but data latency increases and communication bandwidth is limited
Solution Approach 1:
The patent segments the serial data path by introducing parallel communication channels. Specifically, it creates direct point-to-point connections between controller and TAP domains, bypassing the need for sequential traversal through intermediate domains. This segmentation transforms the single serial path into multiple parallel paths, reducing data latency while maintaining universal TAP domain accessibility.
Solution Approach 2:
The patent introduces TMS and TCK signal lines as intermediary communication channels between the controller and TAP domains. These intermediaries carry data directly without requiring traversal through other TAP domains, thus reducing latency. The TMS line serves as a dedicated data path while TCK provides clocking, creating an efficient intermediary communication mechanism.
2Reliability
If data traverses multiple TAP domains serially, then standard JTAG protocol is maintained, but communication bandwidth is reduced
Solution Approach 1:
The patent makes the TMS and TCK signal lines multi-functional. TMS serves both its traditional function of controlling TAP state transitions and its new function as a bidirectional data communication channel. TCK serves both as the clock signal for TAP operations and as a clock for the parallel data transmission. This multi-functionality enables increased bandwidth without requiring additional dedicated pins.
Solution Approach 2:
The patent transitions from one-dimensional serial communication through the TDI/TDO path to another dimension by utilizing the TMS and TCK lines for parallel data transmission. This dimensional change in the communication space allows multiple bits to be transmitted simultaneously, dramatically increasing bandwidth while maintaining compatibility with the standard JTAG protocol structure.
3Loss of time
If TMS and TCK are used for direct data transmission, then data latency is reduced, but the risk of interfering with TAP domain state transitions increases
Solution Approach 1:
The patent employs periodic action by using the TCK clock signal to synchronize data transmission on the TMS line. Data bits are transmitted periodically synchronized with TCK edges, ensuring that state machine logic within TAP domains samples data at appropriate times. This periodic synchronization prevents data corruption and ensures reliable communication without interfering with state transitions.
Solution Approach 2:
The patent implements feedback mechanisms where the controller monitors TAP domain responses and adjusts data transmission timing accordingly. The system uses acknowledgment signals and status feedback from TAP domains to ensure data is transmitted only when the domains are in appropriate states, preventing interference with critical state transitions while maintaining efficient communication.
Data Source
AI summary
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.