JTE Edge Termination Layout for Breakdown Voltage and Compact Width
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Solution Overview
Problem
Conventional power semiconductor devices face limitations in achieving both high current and high speed switching due to material constraints, and the edge termination structure in semiconductor devices often results in reduced breakdown voltage and increased processing complexity.
Innovation Solution
A semiconductor device with an edge termination structure region having a low-concentration semiconductor layer of a first conductivity type on a high-concentration semiconductor substrate, and a second semiconductor layer with a lower impurity concentration in contact with the active region, which mitigates electric field concentration and allows for improved breakdown voltage without a mesa portion, enabling a shorter horizontal length for the edge termination structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an edge termination structure is formed with conventional methods, then breakdown voltage is maintained, but the horizontal width of the edge termination structure region increases
Solution Approach 1:
The patent applies local quality by creating a junction termination extension (JTE) structure with varying impurity concentrations in different regions. The JTE has a first region with higher impurity concentration and a second region with lower impurity concentration, allowing each region to perform its specific function optimally while maintaining overall breakdown voltage and reducing horizontal width
Solution Approach 2:
The patent changes the impurity concentration parameter across different regions of the JTE structure. By having a first region with higher impurity concentration and a second region with lower impurity concentration, the structure achieves both electrical performance and compact dimensions
2Reliability
If an edge termination structure is formed with conventional methods, then breakdown voltage is maintained, but processing complexity increases
Solution Approach 1:
The patent merges the JTE formation process with the existing device fabrication process by using the same ion implantation and annealing steps. The first and second regions of the JTE are formed in sequence using standard processing techniques, reducing overall processing complexity while maintaining breakdown voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances breakdown voltage and reduces the horizontal length of the edge termination structure, addressing the limitations of conventional devices by improving processing accuracy and device performance.
Implementation Method 1
The low-concentration semiconductor layer of a first conductivity type, having a low concentration, and the second semiconductor layer of a second conductivity type, having an impurity concentration that is lower than that of the semiconductor layer, contribute to reducing electric field concentration at the edge termination structure
Data Source
AI summary
A semiconductor device includes, as a semiconductor region in which semiconductor layers are formed, an active region through which current flows and an edge termination structure region outside the active region and in which an edge termination structure is formed. The semiconductor device includes as the semiconductor layers: a drift layer of a first conductivity type and a base layer of a second conductivity type, in contact with the edge termination region; and includes an interlayer insulating film provided on the semiconductor region, on a side thereof where the base layer is formed. The edge termination region has a first semiconductor layer of the second conductivity type, continuous from the base layer and having an outer peripheral end not in contact with the interlayer insulating film, and a second semiconductor layer of the first conductivity type, in contact with the first semiconductor layer and forming a first PN junction therewith.