Power Semiconductor Junction Temperature Sensing via Gate Resistance
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Solution Overview
Problem
Existing methods for estimating junction temperature in power semiconductors are complex, costly, and require individual calibration, making them unsuitable for low-cost industrial applications.
Innovation Solution
A device and method utilizing current pulses injected through the gate path of a power semiconductor, synchronized with its ON state, to measure junction temperature via the internal gate resistance, generating a continuous signal dependent on temperature, which is then adapted for easy measurement and comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual calibration is performed for each power module reference, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent uses a reference module that replicates the electrical characteristics of the power module under test. By measuring the reference module's gate-source voltage under identical conditions, the system obtains temperature data without requiring individual calibration of each module. This copying approach eliminates complex calibration procedures while maintaining measurement accuracy.
Solution Approach 2:
The reference module automatically compensates for variations in gate resistance between different power module references. The system self-adjusts by comparing measurements against the reference module's characteristics, eliminating the need for external calibration equipment or procedures. This self-service mechanism simplifies the overall system while preserving measurement precision.
2Measurement precision
If fast ADC with high resolution is used to monitor voltage samples quickly, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent performs voltage sampling at a predetermined time point after gate voltage application, when the capacitive charging effect has subsided and the measurement is most stable. This preliminary timing strategy allows the use of lower-resolution, slower ADCs while still achieving accurate temperature measurements, thereby reducing device complexity and cost.
Solution Approach 2:
The measurement system uses periodic PWM cycles to apply gate voltage and sample the resulting voltage. By synchronizing measurements with the periodic PWM signal and selecting specific phases within each cycle, the system achieves accurate temperature monitoring without requiring continuously high-speed ADC operation, thus reducing overall system complexity.
3Measurement precision
If voltage sampling is performed quickly after switch opening, then measurement precision is improved, but device complexity increases due to synchronization requirements
Solution Approach 1:
The patent employs feedback from the PWM control signal to synchronize the measurement timing. The same PWM signal that drives the power semiconductor also triggers the voltage sampling and measurement sequence. This feedback-based synchronization ensures measurements are taken at the optimal moment without requiring complex external synchronization circuits, thereby maintaining measurement precision while reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Provides a simple, low-cost, and robust method for junction temperature estimation with reduced calibration effort, suitable for industrial use, and allows for reliable over-temperature detection.
Implementation Method 1
uses the internal gate resistor Rgin as a temperature sensitive electric parameter (TSEP). The junction temperature is estimated from the gate temperature. A sense current Ig is injected through the gate during the PWM. The voltage response Vs is temperature sensitive.
Data Source
Figure 1A~1B
Figure 2
Figure 3~6
AI summary
Device and method for measuring a junction temperature of a power semiconductor (3) using the resistance Rgint (32) of said semiconductor (3) comprising at least: a current injector circuit (5) injecting current pulses Iinj in the gate path of said power semiconductor (3) through the emitter of said power semiconductor, said current injector circuit (5) being driven by a digital injection control circuit (4, 6) to synchronize said current pulses within a stabilized part of ON states of the power semiconductor driver (1) PWM signal driving said power semiconductor (3), a peak detector circuit (7) to record emitter voltage peaks Ve at the terminals of the current injector circuit and generate a continuous signal Vpks dependent of the junction temperature Tj through integration of said voltage peaks, a signal conditioning circuit (8) to adapt the continuous signal Vpks dependent of the junction temperature into a range of 3V to 5V of a measurement system (9).