Junctionless FET Threshold Control via Cap Layer
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Solution Overview
Problem
Junctionless FETs are typically normally-on devices due to the same conductivity type of source/drain and channel regions, requiring complex processes to achieve normally-off operation, and the use of different gate materials for n-type and p-type FETs increases manufacturing costs. Additionally, the miniaturization of devices is approaching physical limits, and there is a need for higher integration density and performance in ICs.
Innovation Solution
A field-effect transistor with a multigate structure and a cap layer made of different material than the channel region, such as an amorphous Si layer, is used between the channel region and the gate insulating film to shift the threshold voltage from normally-on to normally-off operation, allowing for the same gate electrode material to be used for both n-type and p-type junctionless FETs, and utilizing polycrystalline germanium as the channel material for improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a junctionless FET is designed with source/drain and channel regions of the same conductivity type, then the manufacturing process becomes simple and miniaturization is enabled, but the device operates in normally-on mode requiring complex additional processes to achieve normally-off operation
Solution Approach 1:
The patent introduces a cap layer with different material composition (e.g., SiGe, GaAs) or doping concentration than the channel region, thereby changing the electrical parameters at the interface. This modifies the threshold voltage to enable normally-off operation while preserving the junctionless structure's manufacturing simplicity. The cap layer acts as an interface engineering solution that transforms the device's operational state without complicating the fabrication process.
2Reliability
If different gate electrode materials are used for n-type and p-type junctionless FETs to achieve normally-off operation, then the threshold voltage can be controlled, but the manufacturing cost increases due to process complexity
Solution Approach 1:
The patent employs a universal gate electrode material (such as polysilicon or metal) for both n-type and p-type junctionless FETs. The differentiation in threshold voltage control is achieved not through different gate materials but through the cap layer's material composition and doping characteristics. This universal approach to gate electrodes simplifies the manufacturing process, reduces costs, and enables standard CMOS-compatible fabrication while maintaining the ability to control device operation mode.
3Productivity
If the channel width is reduced to about 10 nm to generate large on-state current, then the device performance improves, but the device approaches physical miniaturization limits requiring advanced manufacturing techniques
Solution Approach 1:
The patent utilizes composite material structures, specifically the combination of the cap layer (e.g., SiGe, GaAs) with the silicon channel region. This composite interface enables enhanced carrier mobility and improved on-state current at scaled dimensions. The different band structures and material properties of the cap layer and channel region work synergistically to maintain high performance even as the channel width is reduced to 10 nm, thereby addressing the challenges of physical miniaturization limits.
Data Source
AI summary
According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.