Junctionless FinFET Sidewall Channel for Device Stability
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Solution Overview
Problem
Current semiconductor manufacturing methods face stability issues due to continuous reduction in gate critical dimensions, leading to interactions between PN junctions and devices, which affect the performance and reliability of metal-oxide-semiconductor (MOS) devices.
Innovation Solution
The method involves forming a semiconductor device with a fin structure, where a fully-depleted semiconductor layer is created on the sidewalls of the fin using a material different from the fin, and a gate dielectric and gate electrode layer are formed to increase gate width and improve stability, using a silicon-on-insulator (SOI) substrate and selective epitaxial deposition to ensure uniformity and reduce interference between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate critical dimension is continuously reduced to increase device integration, then device density increases, but device stability deteriorates due to interactions between PN junctions and devices
Solution Approach 1:
The semiconductor device is divided into distinct functional regions with a fully-depleted semiconductor layer forming the channel and source/drain regions separated by a junctionless structure. This segmentation eliminates the traditional PN junction and creates independent functional zones, preventing harmful interactions between adjacent regions while maintaining high device density.
Solution Approach 2:
The invention extracts and removes the traditional PN junction structure from the device architecture. By transitioning to a junctionless fully-depleted semiconductor layer, the harmful interactions between PN junctions and adjacent devices are eliminated, while the essential transistor functionality is preserved through the gate-controlled channel formation.
2Manufacturing precision
If conventional manufacturing methods are used with continuous process node reduction, then manufacturing complexity increases, but device stability deteriorates
Solution Approach 1:
Instead of continuing to reduce gate critical dimensions to achieve smaller process nodes, the invention inverts the approach by using a junctionless fully-depleted structure that achieves high integration density without relying on further dimensional reduction. This reverses the conventional scaling paradigm and eliminates the associated stability issues.
Solution Approach 2:
The invention changes the fundamental structural parameters of the semiconductor device by transitioning from a conventional PN junction structure to a junctionless fully-depleted structure. This parameter change enables continued process node reduction while maintaining device stability, as the new structure is not subject to the same interaction problems that limit conventional devices.
3Ease of manufacture
If traditional MOS device structures are used, then manufacturing process is simpler, but device stability and performance are poor due to PN junction interactions
Solution Approach 1:
The fully-depleted semiconductor layer is formed as a preliminary structure before final device assembly, creating a junctionless channel region that pre-prevents harmful PN junction interactions. This preliminary formation of the depleted layer ensures device stability is built into the structure from the beginning, while the overall manufacturing process remains compatible with existing semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability of semiconductor devices by reducing electric field, improving transconductance, and achieving better short-channel characteristics, while increasing gate width and minimizing interference between channel regions, thus improving overall device performance and reliability.
Implementation Method 1
forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin
Data Source
AI summary
A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.