Junction-less Transistor Fin Structure Reducing Capacitance and Self-Heating

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Solution Overview

Problem

Conventional junction-less transistor devices face issues with high junction capacitance and self-heating effects due to direct contact with the substrate and the presence of insulating layers, respectively.

Innovation Solution

A junction-less transistor design featuring a buried dielectric layer with a fin structure, where source/drain structures are formed on the buried dielectric layer, and a doped region is created through the buried dielectric layer to reduce junction capacitance and avoid self-heating, with a semiconductor layer having regions of varying doping concentrations to facilitate efficient current flow and minimize leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If source/drain structures are formed on bulk silicon substrate, then device integration is achieved, but junction capacitance increases

Engineering Contradiction:

Improvejunction capacitanceVSAvoiddevice structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The device structure is segmented by introducing a buried dielectric layer that separates the source/drain structures from the bulk silicon substrate. This segmentation isolates the active region, reducing parasitic junction capacitance while maintaining device functionality through the fin structure configuration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A buried dielectric layer is introduced as an intermediary between the source/drain structures and the bulk silicon substrate. This intermediate layer acts as an electrical isolator, reducing junction capacitance without requiring complete removal of the substrate, thus balancing performance improvement with structural simplicity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If insulating layer is present in junction-less transistor, then device structure is simplified, but self-heating effect increases

Engineering Contradiction:

Improvedevice structureVSAvoidself-heating

Core Design Contradiction:

Ease of manufactureVSTemperature

Solution Approach 1:

Instead of using a complete insulating layer, the invention applies a localized fin structure configuration where the substrate is exposed only in the active channel region. This local quality approach maintains thermal pathways where needed while providing electrical isolation where required, reducing self-heating effects without complicating the overall device structure.

Inventive Principle:

Principle #3Local quality

3Power

If fin structure is used in FET, then drive current increases, but parasitic resistance increases

Engineering Contradiction:

Improvedrive currentVSAvoidparasitic resistance

Core Design Contradiction:

PowerVSObject-affected harmful factors

Solution Approach 1:

The invention transitions from a planar FET structure to a three-dimensional fin structure, where the channel extends vertically from the substrate. This dimensional change increases the effective channel width and drive current capability while the exposed substrate configuration minimizes parasitic resistance by reducing the area of high-field regions at the source-drain junctions.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces junction capacitance, minimizes self-heating, and enhances performance by improving current flow, integration, and reducing power consumption while maintaining high temperature and radiation resistance.

Implementation Method 1

a doped region (130) that extends into the substrate though a portion of the buried dielectric layer... reduce junction capacitance

Methodology Applied

Scientific EffectJunction capacitance reduction: Capacitance

Implementation Method 2

source/drain structures are formed on the buried dielectric layer, and a doped region is created through the buried dielectric layer to reduce junction capacitance and avoid self-heating

Methodology Applied

Scientific EffectSelf-heating reduction: Thermal Insulation

Implementation Method 3

a semiconductor layer having regions of varying doping concentrations to facilitate efficient current flow and minimize leakage

Methodology Applied

Scientific EffectCurrent flow: Conduction (electrical)

Implementation Method 4

a gate electrode structure wrapping around a portion of the semiconductor layer

Methodology Applied

Scientific EffectField effect transistor operation: Electric Field

Data Source

PatentUS8928082B2JLT (junction-less transistor) device and method for fabricating the same

Publication Date: 2015.01.06 SEMICON MFG INT (SHANGHAI) CORP

AI summary

A method for fabricating a junction-less transistor device that includes a substrate, a buried dielectric layer having a fin structure on the substrate, a doped region formed through the buried dielectric layer in the substrate, a semiconductor layer overlying the buried dielectric layer and the doped region, a gate structure on the semiconductor layer, and source/drain regions in the semiconductor layer at opposite sides of the gate structure. The semiconductor layer includes first, second, third regions, with the second region interposed between the first and second regions and disposed underneath the gate electrode structure. The first, second, and third regions have a same doping polarity. The second region has a doping concentration less than those of the first and second regions. The second region and the doped region have opposite doping polarities. The second region has a groove in contact with a bottom portion of the gate structure.