Keeper-Free Clock Gating Circuit for Low-Capacitance Enable Timing
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Solution Overview
Problem
Existing Integrated Clock Gating (ICG) cells face challenges in achieving minimal setup time for enable signals, leading to inefficiencies in clock power reduction and potential functional failures due to glitches and increased dynamic capacitance.
Innovation Solution
A keeper-free ICG cell design utilizing OR-AND-Invert (OAI) and AND-OR-Invert (AOI) gate configurations with reduced hold time and minimized transistor count, which effectively gates the clock signal with lower switching power and dynamic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ICG cell designs are used, then clock gating functionality is provided, but setup time for enable signals is not minimal leading to functional failures and glitches
Solution Approach 1:
The ICG cell is segmented into distinct functional blocks: enable signal generation logic, clock gating logic, and output buffering. This segmentation allows optimization of each block independently, achieving minimal setup time in the enable signal generation while maintaining overall cell functionality without excessive complexity.
Solution Approach 2:
The enable signal is generated and prepared in advance through dedicated logic paths before the clock edge arrives. This preliminary action ensures that the enable signal is ready well before the critical clock transition, eliminating setup time violations and preventing functional failures.
2Loss of energy
If traditional ICG cell designs are used, then clock gating is achieved, but dynamic capacitance is increased leading to higher power consumption
Solution Approach 1:
Unnecessary capacitive loads are extracted and removed from the critical signal paths. The design eliminates redundant buffering and minimizes the capacitance that must be charged and discharged during clock transitions, directly reducing dynamic power consumption while maintaining clock gating functionality.
Solution Approach 2:
The design changes the capacitance parameters by using optimized transistor sizing and minimal buffering structures. This reduces the dynamic capacitance value itself, leading to lower power consumption during switching operations while preserving the required signal drive strength.
3Loss of energy
If traditional ICG cell designs are used, then clock power reduction is attempted, but functional failures occur due to glitches
Solution Approach 1:
The design incorporates prior cushioning by generating the enable signal well in advance of the clock edge and using synchronized logic paths. This timing margin acts as a cushion that prevents glitches from propagating to the clock output, ensuring functional reliability while still achieving power reduction through selective gating.
4Area of stationary object
If minimal transistor count is used, then device area is reduced, but setup time and hold time requirements become more challenging
Solution Approach 1:
Multiple functions are merged into compact logic structures. The enable signal generation, clock gating control, and output buffering are combined in an integrated manner that minimizes the number of transistors required while maintaining precise timing control through shared logic paths and synchronized operation.
Solution Approach 2:
The design uses dynamic logic techniques where transistor switching is optimized to provide sufficient timing margins. By dynamically controlling the switching sequences and using clocked logic structures, the cell achieves both compact area and precise timing control without requiring excessive transistor count.
Data Source
AI summary
An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.