Kelvin Test Structure for Via Chamfering Depth Detection
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Solution Overview
Problem
Traditional methods for detecting chamfering in semiconductor wafers, such as optical via critical dimension measurements and cross-sectional cuts, are either non-destructive but not applicable in production lines or destructive and unable to determine the depth of chamfering, leaving insufficient process margin and potential for wafer defects.
Innovation Solution
A semiconductor test device and method using Kelvin testable structures with upper and lower metal plates and vias, allowing for differential resistance measurement between measurement and reference vias to detect chamfering depth and provide process margin metrics, enabling in-line monitoring and adjustment of manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional optical via critical dimension measurements are used, then measurement of via diameter is possible, but the depth of chamfering cannot be determined
Solution Approach 1:
The patent replaces optical measurement methods with electrical resistance measurement. By measuring the resistance of the via and comparing it to a reference resistance, the system can determine chamfer depth information that optical methods cannot provide. The resistance measurement serves as an electrical analog that captures dimensional information about the via structure including chamfer depth.
2Measurement precision
If traditional cross sectional cuts are used, then all dimensions including chamfer depth can be measured, but the method is destructive and cannot be applied in production line
Solution Approach 1:
The patent creates an electrical copy of the via's physical dimensions through resistance measurement. Instead of physically cutting and examining the via, the system measures electrical resistance which correlates to the via's dimensional properties including chamfer depth. This non-destructive electrical measurement allows production line monitoring without damaging the semiconductor wafer.
Solution Approach 2:
The patent replaces the mechanical cross-sectional cutting method with an electrical resistance measurement system. This substitution enables non-destructive measurement that can be performed in-line during production, maintaining measurement precision while eliminating the destructiveness and complexity of physical sectioning.
3Device complexity
If no chamfer depth monitoring is implemented, then production process is simpler, but process margin cannot be determined leading to potential wafer defects
Solution Approach 1:
The patent implements a feedback mechanism where the measured via resistance is compared to a reference resistance to determine chamfer depth and process margin. This feedback loop provides real-time information about the manufacturing process state, enabling adjustments to maintain reliability without requiring complex monitoring systems.
Solution Approach 2:
The patent replaces complex physical monitoring systems with simple electrical resistance measurements. By using resistance as a proxy for chamfer depth, the system achieves reliable process margin determination with minimal added complexity, avoiding the need for intricate sensing or imaging equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables early detection of chamfering and monitoring of process margin, reducing wafer defects and allowing for real-time tuning of manufacturing processes to prevent failures, with improved accuracy and reduced complexity in production line implementation.
Implementation Method 1
The first Kelvin testable structure includes an upper metal plate, one measurement via under and electrically connected to the upper plate and a lower metal island electrically connected to the one measurement via
Implementation Method 2
The resistance of the measurement via is determined by applying a first current to either the lower metal island or the upper metal plate and determining the voltage drop between the upper metal plate and the lower metal island
Data Source
AI summary
Aspects of the present disclosure include a semiconductor test device and method. The test device includes a first Kelvin testable structure and a second Kelvin testable structure. The first Kelvin testable structure includes an upper metal plate, a plurality of dummy vias and one measurement via under and electrically connected to the upper plate and a lower metal island electrically connected to the one measurement via. The second Kelvin testable structure includes an upper reference metal plate, a reference via under and electrically connected to the upper reference metal plate, and a lower metal reference island electrically connected to the reference via.