L-Shaped FEOL Capacitor for Substrate Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern flash memory technologies require high voltages for erase and program operations, which are achieved using integrated charge pumps with planar PIP capacitors, but these capacitors have a smaller height than select and control gates, leading to substrate damage during fabrication due to inadequate masking layer protection.
Innovation Solution
A non-planar FEOL capacitor with a charge trapping dielectric layer is developed, featuring electrodes with heights equal to those of select and control gates, and a charge trapping dielectric layer with an 'L' shape, providing enhanced capacitance and eliminating the need for patterning a capacitor top plate, thus protecting the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar PIP capacitors are used in integrated charge pumps, then the capacitor structure is simple and fabrication is easy, but the capacitor height is smaller than select and control gates, leading to substrate damage during fabrication
Solution Approach 1:
The patent transitions from planar (2D) capacitor structure to a three-dimensional structure where the capacitor extends vertically to the same height as select and control gates. This dimensional change allows the capacitor to maintain ease of manufacture while achieving adequate height for substrate protection during fabrication processes.
Solution Approach 2:
The capacitor structure is divided into multiple functional regions including a bottom electrode, dielectric layer, and top electrode, with each layer formed through separate deposition and patterning steps. This segmentation allows independent optimization of each component while maintaining overall structural integrity and protection capability.
2Ease of manufacture
If planar PIP capacitors are used, then fabrication process is straightforward, but capacitance relative to footprint is limited
Solution Approach 1:
By extending the capacitor structure vertically in the third dimension, the patent increases the effective capacitance area without proportionally increasing the planar footprint. The vertical extension of dielectric and electrode layers provides additional capacitance storage volume, thereby improving capacitance density while maintaining a compact lateral footprint.
Solution Approach 2:
The capacitor structure is nested within the existing memory cell architecture, with the capacitor vertically integrated alongside select gates and control gates. This nested arrangement allows the capacitor to utilize the vertical space already allocated in the device structure, maximizing capacitance within the available footprint without requiring additional lateral area.
3Manufacturing precision
If capacitor top plate patterning is performed, then capacitor positioning is precise, but fabrication complexity and cost increase
Solution Approach 1:
The patent merges the capacitor electrode formation process with the existing gate electrode formation processes. The same electrode deposition and patterning steps used for creating select and control gates are simultaneously used to form the capacitor electrodes, eliminating the need for separate capacitor top plate patterning operations and reducing overall fabrication complexity.
Solution Approach 2:
The capacitor structure utilizes the same materials and fabrication processes as the memory cell gates, making the fabrication equipment and process steps universal across different device components. This multi-functionality approach allows a single set of process tools and parameters to produce both high-performance memory gates and precise capacitor structures without requiring additional specialized processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The non-planar FEOL capacitor mitigates substrate damage, offers high capacitance relative to its footprint, and reduces fabrication costs by eliminating the need for patterning, while maintaining performance comparable to existing solutions.
Implementation Method 1
The non-planar FEOL capacitor provides a capacitance that is relatively high in comparison to its footprint
Implementation Method 2
A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode
Data Source
AI summary
The present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. In some embodiments, the non-planar FEOL capacitor has a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer has an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction. A second electrode is arranged onto the lateral component and is separated from the first electrode by the first component.