L-Shaped Semiconductor Layer for Organic Thin Film Transistors
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Solution Overview
Problem
Conventional organic thin film transistors face challenges with low dielectric constant in the organic insulating layer, leading to larger device sizes and complexity in design and manufacturing, especially for high-resolution products, and the dual gate structure requires multiple lithography and etching processes, increasing complexity and time.
Innovation Solution
The design includes a dual gate structure with a drain electrode, semiconductor layer, source electrode, and gate insulator, where the semiconductor layer has an L-shaped cross-section, and the source electrode extends opposite to the drain electrode, with the gate electrode positioned on the gate insulator, allowing for reduced pixel area occupation, increased capacitance, and reduced parasitic capacitance, while simplifying the manufacturing process by eliminating complex contact hole processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the dielectric constant of the organic insulating layer is increased, then the transistor size can be reduced, but the manufacturing complexity increases
Solution Approach 1:
The gate insulator extends not only horizontally between source and drain electrodes but also vertically along the side surfaces of the semiconductor layer. This three-dimensional configuration increases the effective gate area without proportionally increasing the planar footprint, thereby reducing transistor size while avoiding excessive manufacturing complexity by utilizing the vertical dimension.
Solution Approach 2:
The gate insulator is positioned within the structure formed by the source, drain, and semiconductor layer, wrapping around the semiconductor layer's side surfaces. This nested arrangement maximizes the gate insulator's coverage area within the confined transistor structure, achieving higher capacitance density and smaller device footprint.
2Reliability
If a dual gate structure is adopted, then stability is improved, but manufacturing complexity and time increase due to multiple lithography and etching processes
Solution Approach 1:
The gate insulator structure combines both front gate and back gate functions into a single continuous layer that covers the top surface and side surfaces of the semiconductor layer. This unified structure provides dual-gate control for improved stability while simplifying manufacturing by eliminating the need for separate lithography and etching processes for multiple gates.
Solution Approach 2:
The gate insulator serves multiple functions simultaneously: it acts as the dielectric layer for front gate control, provides back gate control through side surface coverage, and protects the semiconductor layer. This multi-functionality achieves dual-gate stability benefits while reducing manufacturing complexity.
3Area of stationary object
If the transistor size is reduced for high resolution products, then display area increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
By extending the gate insulator vertically along the side surfaces of the semiconductor layer, the effective gate area is increased without proportionally increasing the planar dimensions. This allows transistor size reduction for higher resolution displays while maintaining adequate gate control and reducing the impact of manufacturing precision variations.
Data Source
AI summary
An organic thin film transistor includes a drain electrode, a semiconductor layer, a source electrode, a gate insulator, and a gate electrode. A horizontal portion and a vertical portion of the semiconductor layer are respectively located on a top surface and an end surface of the drain electrode, and the drain electrode protrudes from the horizontal portion in a first direction. The source electrode is disposed along a surface of the semiconductor layer. The source electrode has an extending portion that extends in a second direction opposite to the first direction. The gate insulator is disposed along a top surface and two side surfaces of a stacked structure defined by the drain electrode, the semiconductor layer, and the source electrode. The gate electrode is located on the gate insulator, and a portion of the gate insulator is between the stacked structure and the gate electrode.