L-Type Spacer Design for Semiconductor Gate Stress Reduction
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Solution Overview
Problem
Semiconductor devices face challenges with gate spacer stress and physical and chemical damage to silicide regions, which affect the stability and conductivity of the devices, particularly due to the increasing density and heat-related stresses during manufacturing.
Innovation Solution
A semiconductor device design that includes an L-type spacer adjacent to the gate pattern with an extended end to the substrate surface, source/drain silicide regions formed between the L-type spacer and isolation regions, and via plugs electrically connected to these regions, along with an interlayer dielectric layer that fills the space between the via plugs, effectively eliminating the need for a conventional gate spacer and reducing stress on the silicide regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a conventional gate spacer is used, then the gate structure is stable, but stress is generated on the silicide regions causing damage and characteristic deterioration
Solution Approach 1:
The patent removes the conventional gate spacer structure entirely and replaces it with an L-type spacer that extends to the substrate surface. This extraction of the harmful gate spacer element eliminates the stress it generates on the silicide regions while maintaining necessary structural functions through the alternative L-type spacer design.
Solution Approach 2:
Instead of using a horizontal gate spacer that sits atop the gate structure, the patent inverts the approach by using a vertical L-type spacer that extends from the gate sidewall down to the substrate surface. This inversion changes the stress distribution pattern and eliminates the harmful compressive stress on the silicide regions.
2Object-affected harmful factors
If the gate spacer is removed to eliminate stress, then stress on silicide regions is reduced, but the silicide region becomes exposed and vulnerable to physical and chemical damage
Solution Approach 1:
The L-type spacer acts as an intermediary protective structure that extends vertically from the gate sidewall to the substrate surface. It provides physical and chemical protection to the silicide region without generating the harmful stress associated with conventional gate spacers, thus mediating between the need for protection and the need for stress elimination.
Solution Approach 2:
The L-type spacer is formed using a composite structure combining multiple materials including a first spacer material and a second spacer material with different etch selectivities. This composite approach allows the spacer to provide both mechanical protection and process compatibility during manufacturing.
3Reliability
If metal contacts the semiconductor substrate directly, then conductivity is improved, but voids are formed making the structure unstable
Solution Approach 1:
The patent changes the material parameter at the metal-substrate interface by introducing a silicide layer. This parameter change allows the structure to maintain both high conductivity (like metal) and structural stability (like semiconductor), resolving the contradiction between conductivity improvement and structural stability.
Data Source
AI summary
A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.