Level One Cache Extension Using Level Two Memory Portion
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Solution Overview
Problem
Modern computing devices face limitations in memory access due to the small size of level one cache, which restricts the effective memory size and access speed, as level two memory is not efficiently utilized.
Innovation Solution
A selected portion of level two memory is treated as an extension of level one memory, allowing memory access requests to be directed to it in parallel, thereby increasing effective memory size without increasing access time, by being physically proximal to level one memory to reduce wiring length and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of level one cache is increased, then the effective memory size is improved, but the physical space and wiring length increase causing access time to worsen
Solution Approach 1:
The patent extends the memory hierarchy by utilizing a portion of level two cache that is physically located adjacent to level one cache. This spatial reorganization allows the system to access what is effectively a larger memory space without increasing the wiring length or access time, as the additional memory capacity is obtained by utilizing unused or underutilized space in the existing memory structure rather than expanding physically.
Solution Approach 2:
The patent makes a portion of level two cache serve dual purposes: it functions as part of the level two cache hierarchy while simultaneously operating as an extension of level one cache. This multi-functionality allows the same physical memory space to provide both L2 caching benefits and L1-speed access capabilities, effectively increasing the usable memory size without adding dedicated L1 memory resources.
2Quantity of substance
If level two memory is utilized as extension of level one memory, then the effective memory size is improved, but the memory hierarchy complexity increases
Solution Approach 1:
The patent merges a portion of level two cache with level one cache to create a unified memory access structure. By physically locating part of L2 adjacent to L1 and enabling simultaneous access to both, the system combines the benefits of large capacity (from L2) with fast access (from L1) without creating a complex multi-layer hierarchy. The merge is achieved through shared address decoding and parallel access paths that simplify the overall memory control logic.
3Loss of time
If a selected portion of level two memory is physically located proximal to level one memory, then the access time is reduced, but the wiring space and physical area increase
Solution Approach 1:
The patent utilizes the vertical or lateral dimension of the semiconductor substrate by placing a portion of level two cache in the same physical plane or adjacent location as level one cache. This three-dimensional spatial arrangement allows memory cells to be accessed with minimal wire length while maintaining the hierarchical memory structure, effectively obtaining fast access without proportionally increasing the wired connection area.
Data Source
AI summary
A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.