Memory Adressing/Allocation/Relocation TRIZ Cases
- Memory Slot Enablement via Identifier Comparison
A computing system detects disabled memory module slots during boot and compares current identifiers against stored values to restore access.
- Non-volatile Memory Probing for Parameter Detection
A system-on-chip probes non-volatile memory with varying address cycles to determine valid access parameters.
- Extending localStorage for Remote Data Sharing
Extends browser localStorage to store client content remotely, bypassing the 5 MB quota limit and enabling cross-device data sharing.
- PCIe Network Switch Non-Transparent Bridge Memory Access
Non-transparent bridges in a PCIe network switch enable direct memory access between servers, eliminating local storage latency and congestion.
- Motherboard Memory Slot Interface Controller Dynamic Addressing
Dynamic pin control generates unique access addresses for each memory slot group, eliminating address conflicts and removing the need for external multiplexers.
- Mapping Client Integration for Shared Storage I/O Elimination
A mapping client integrated into a hypervisor caches shared storage objects to eliminate redundant physical I/O operations.
- Progressive Image Data Loading with Pre-Allocated Memory Addresses
A progressive volume loading approach stores image data sections at addresses corresponding to their original locations in memory.
- Capacity Index for Fast Row Page Lookup in In-Memory Databases
A capacity index records page data volume changes to map row positions directly to storage pages.
- Mixed Compiler for IC Memory and Logic Units
A mixed compiler configures memory and logic units in an integrated circuit simultaneously using predefined parameters.
- Interruptible Read-Modify-Write Memory Interface for Low Latency
An interruptible read-modify-write memory interface allows higher priority requests to temporarily suspend pending operations.
- Controller Interleaving Data Across Multiple Memory Devices
A controller interleaves user data sets across first and second memory devices to enhance system performance.
- Secure Memory Segmentation for Contactless Applications
Application memory segmentation using shared secret keys to reserve private workspaces for contactless applications.
- Speculative Processor Replay Bit Mechanism
A processor miss buffer uses a replay bit to control execution mode transitions during speculative instruction processing.
- Memory Fetch Granule for Real-Time Agents
Grouping memory requests into fetch granules prevents head of line blocking and reduces latency in distributed subsystems.
- Data Transfer Controller Parallel Arbitration
Segmented transfer controllers enable parallel operations, resolving bottlenecks from heavy memory coupling.
- Controller- opaque NVM command scripts for host debugging
Command scripts execute arbitrary operations on non-volatile memory without controller understanding, enabling advanced testing and debugging.
- Unified Memory Architecture for Distributed Graphics Processing
A unified memory architecture allocates virtual pages across distributed graphics processors to consolidate closed page lists and reduce memory footprint.
- Virtual Address Translation for EEPROM Diagnostic Access
Control circuit translates virtual addresses to physical EEPROM locations, enabling diagnostic data access without additional hardware interfaces.