Mixed Compiler for IC Memory and Logic Units
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Solution Overview
Problem
The existing integrated circuit design process is time-consuming due to iterative optimization of memory and logic units to meet performance, power, and area criteria, as the memory and logic compilers operate sequentially rather than concurrently.
Innovation Solution
A unified memory structure model and mixed compiler approach, where memory and logic units are compiled and positioned simultaneously using predefined parameters, parsed to generate mapping candidates, and selected based on key performance indicators, allowing for concurrent selection and placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory compiler and logic compiler are performed sequentially in iterative optimization, then the design can meet performance, power, and area criteria, but the design process becomes time-consuming
Solution Approach 1:
The patent merges the memory compiler and logic compiler into a unified compiler that performs both memory unit selection and logic unit selection simultaneously. This integration allows the system to evaluate and optimize both memory and logic configurations in a single iterative cycle rather than sequentially, reducing the total number of iterations required and thus the overall design time while maintaining the ability to meet KPI criteria.
Solution Approach 2:
The patent implements preliminary action by pre-defining multiple memory units with different memory types and pre-defining multiple logic units with different logic types before the compilation process. This pre-preparation of candidate units allows the unified compiler to directly evaluate and select from predefined options during the compilation process, avoiding time-consuming iterative optimization and enabling faster design meeting of performance, power, and area requirements.
2Reliability
If iterative optimization is performed to meet performance, power, and area criteria, then the design quality improves, but the compilation process becomes more complex and time-consuming
Solution Approach 1:
The patent segments the compilation process into distinct phases: a memory unit selection phase that evaluates memory units based on performance, power, and area criteria, and a logic unit selection phase that independently evaluates logic units using the same criteria. This segmentation allows each phase to operate independently and efficiently, reducing the overall complexity of the compilation process while maintaining high design quality through systematic evaluation of multiple candidate units.
3Reliability
If multiple memory units and logic units are selected through iterative processes, then the optimal configuration is achieved, but the time required for optimization increases significantly
Solution Approach 1:
The patent uses copying by creating virtual models of memory units and logic units with predefined characteristics. Instead of physically testing each configuration combination, the system copies the essential properties of multiple candidate units into virtual representations and evaluates them through simulation and analysis. This allows the system to rapidly assess numerous configuration possibilities and identify optimal combinations without the time cost of exhaustive physical testing, thereby achieving optimal configuration with significantly improved optimization speed.
Data Source
AI summary
A method for configuring a plurality of memory units and a plurality of logic units in an integrated circuit includes providing a plurality of predefined parameters of the plurality of memory units, parsing the plurality of predefined parameters to generate a plurality of parsed parameters, compiling the plurality of memory units and the plurality of logic units at the same stage to generate a plurality of candidates of mapping results according to the plurality of parsed parameters, selecting a candidate of the mapping results from the plurality of candidates of the mapping results, and disposing the plurality of memory units and the plurality of logic units onto the integrated circuit according to the candidate of the mapping results.