Mask ROM Layout Verification via Digital Bitmap Comparison
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Solution Overview
Problem
The high cost and long turnaround time associated with manufacturing mask ROMs, due to the expensive process of creating photo masks and correcting errors in the circuit patterns, necessitate a more efficient method for verifying the layout of mask ROMs to reduce production time and costs.
Innovation Solution
A method is developed to verify the layout of mask ROMs by generating coordinate data of bit determining units from layout design data, comparing it with bitmap data and source ROM code, and identifying error cells, thereby reducing verification time significantly while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional photo mask manufacturing method is used to verify mask ROM layout, then verification accuracy is maintained, but verification time increases from seconds to weeks and manufacturing cost increases
Solution Approach 1:
The patent creates a digital copy (bitmap data) of the layout design data to represent the mask ROM circuit pattern. This digital copy can be processed and verified rapidly without requiring physical photo mask manufacturing, thus maintaining verification accuracy while dramatically reducing verification time from weeks to seconds
Solution Approach 2:
The patent replaces the mechanical/photochemical process of physical photo mask manufacturing with an automated computer-based comparison system. The system uses software to compare bitmap data with source ROM code, substituting the traditional mechanical verification process with an electronic automation process that achieves the same verification accuracy much faster
2Reliability
If physical photo mask is manufactured for mask ROM production, then ROM code can be stored, but manufacturing cost increases and turnaround time increases
Solution Approach 1:
The patent performs layout verification as a preliminary action before photo mask manufacturing. By using automated comparison of bitmap data with source ROM code, the system identifies and corrects errors in the layout design data before committing to expensive physical mask production, thereby reducing manufacturing costs while ensuring reliable ROM code storage
Solution Approach 2:
The patent uses digital copying and comparison methods to verify the layout design data against the source ROM code. This digital verification process allows multiple iterations and corrections without incurring additional manufacturing costs, unlike physical photo mask production where each correction requires a new mask
3Manufacturing precision
If traditional verification method is used, then layout compliance can be checked, but turnaround time from designing to production increases
Solution Approach 1:
The patent replaces traditional manual or semi-automated layout verification methods with an automated computer-based system that compares bitmap data with source ROM code. This substitution maintains layout compliance verification accuracy while dramatically improving productivity by reducing turnaround time from weeks to seconds
Solution Approach 2:
The patent enables continuous automated verification processing where the computer system can rapidly compare layout design data with source ROM code without interruption. This continuous processing capability eliminates the delays associated with traditional batch processing or manual verification methods, thereby improving turnaround time while maintaining verification accuracy
Data Source
AI summary
A method of verifying a layout of a mask read only memory (ROM) includes: receiving source ROM code, bitmap data, and layout design data of the mask ROM; generating coordinate data of a bit determining unit based on the layout design data; and determining an error cell based on the coordinate data of the bit determining unit, the bitmap data, and the source ROM code.