Pseudo-Multi-Ported Cache Bandwidth via SRAM Segmentation
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Solution Overview
Problem
Existing cache memory systems using single ported SRAMs face limitations in supporting multiple simultaneous load and store operations due to their single ported nature, which restricts bandwidth and increases latency, while multi-ported SRAMs are costly and require more silicon area, and pseudo dual ported SRAMs suffer from performance degradation during simultaneous operations.
Innovation Solution
A pseudo-multi-ported cache system is designed using multiple single ported SRAMs, where additional tag memory is added to support multiple simultaneous store operations, and cache data memory utilizes multiple SRAM devices for interleaving, allowing simultaneous store and load operations with increased bandwidth without significant increases in silicon area or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-ported SRAMs are used to support multiple simultaneous load and store operations, then bandwidth and operational capability are improved, but silicon area and cost increase
Solution Approach 1:
The cache data memory is divided into multiple separate single-ported SRAM devices, each handling a specific portion of the address space through interleaving. This segmentation allows multiple simultaneous operations without requiring a single complex multi-ported SRAM, thus achieving high bandwidth while controlling silicon area usage.
Solution Approach 2:
Instead of increasing the port count dimension of a single SRAM device, the patent adds the dimension of multiple SRAM devices working in parallel, each accessed through different address spaces. This dimensional shift from single-device multi-ported to multi-device single-ported achieves the same functional goal with different resource implications.
2Adaptability or versatility
If pseudo dual ported SRAMs are used to enable simultaneous operations, then operational capability is improved, but performance degrades during simultaneous operations
Solution Approach 1:
The cache system is segmented into multiple independent single-ported SRAM devices, each capable of handling store operations independently. This segmentation eliminates the performance degradation associated with shared ports in pseudo dual-ported SRAMs, as each SRAM device operates independently without contention.
Solution Approach 2:
The patent introduces a write buffer as an intermediary component that decouples the store operations from the SRAM devices. This intermediary allows multiple store operations to be queued and then written to the SRAM devices in a controlled manner, maintaining performance while enabling simultaneous operations.
3Area of stationary object
If single ported SRAMs are used, then cost and silicon area are reduced, but bandwidth and operational capability are limited
Solution Approach 1:
Multiple single-ported SRAM devices are merged into a unified cache data memory structure through address interleaving. This merging allows the system to achieve multi-ported functionality and high bandwidth by combining the capabilities of multiple simpler SRAM devices, thus maintaining low individual device complexity while achieving high overall performance.
Solution Approach 2:
The patent transitions from a single SRAM device to multiple SRAM devices accessed through different address spaces. This dimensional change from one device to many devices enables the system to overcome the bandwidth limitations of single-ported SRAMs while keeping each individual device simple and cost-effective.
4Adaptability or versatility
If additional tag memory is added to support multiple simultaneous store operations, then operational capability is improved, but device complexity increases
Solution Approach 1:
The tag memory is segmented into multiple separate tag SRAM devices, with each tag SRAM associated with a specific data SRAM device. This segmentation allows each tag SRAM to independently manage tags for its corresponding data SRAM, enabling multiple simultaneous store operations without requiring a single complex multi-ported tag memory structure.
Data Source
AI summary
A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.