Pixel I/O Unit Subframe Alignment for Frame Buffer Throughput
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Solution Overview
Problem
Existing parallel processing architectures, particularly SIMD systems, face challenges in efficiently processing large image frames due to limitations in data throughput and alignment of pixel data, leading to redundant writes and edge effects during subframe processing.
Innovation Solution
A digital data processing system that employs a SIMD array processor with a pixel I/O unit for concurrent data movement and conversion, utilizing a frame buffer with 64-bit data words and SIMD caches for optimal data alignment and transfer, allowing for efficient construction and processing of subframe lines within image frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel data is transferred using conventional memory access methods, then data throughput is limited, but processing speed and productivity are improved through SIMD parallel processing
Solution Approach 1:
The frame buffer is divided into multiple banks, and pixel data is segmented into subframes that can be processed in parallel. Each bank handles specific portions of the data, allowing concurrent access and transfer operations across multiple memory banks simultaneously, thereby increasing overall data throughput without compromising transfer speed.
Solution Approach 2:
The patent introduces a temporal dimension to data transfer by implementing double buffering and alternating between even and odd frame buffers. This allows data transfer and processing to occur in overlapping time periods, effectively doubling the throughput while maintaining the same physical transfer bandwidth.
2Productivity
If pixel data is not aligned properly, then memory access is simplified, but redundant writes and edge effects occur during subframe processing
Solution Approach 1:
The system performs preliminary alignment of pixel data at the frame buffer level before data enters the processing pipeline. By pre-aligning pixels to word boundaries and organizing data into properly formatted subframes, the system eliminates the need for corrective alignment operations during processing, preventing redundant writes and edge effects while maintaining high processing efficiency.
Solution Approach 2:
The patent introduces intermediary components including frame buffer controllers and data alignment logic that act as mediators between the raw pixel data and the processing elements. These intermediaries ensure proper alignment and formatting of data before it reaches the SIMD processors, thereby maintaining precision without complicating the core processing architecture.
3Productivity
If the frame buffer uses simple memory structure, then device complexity is reduced, but data alignment and subframe construction become inefficient
Solution Approach 1:
The frame buffer is segmented into multiple independently addressable banks, each capable of handling specific subframe operations. This segmentation allows parallel construction of multiple subframes simultaneously, dramatically improving construction efficiency. The modular bank structure adds complexity only at the organizational level while keeping individual bank operations simple and efficient.
Solution Approach 2:
The patent implements a nested structure where subframes are nested within frame buffers, and pixel data is nested within subframes in a hierarchical organization. This nesting allows efficient manipulation of data at multiple levels of abstraction, enabling rapid subframe construction by simply assembling pre-organized pixel groups without requiring complex reconfiguration of the underlying memory structure.
Data Source
AI summary
System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.