Motherboard Memory Slot Interface Controller Dynamic Addressing
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Solution Overview
Problem
Conventional motherboards are limited in utilizing memory slots beyond four due to repeated access addresses, leading to incomplete utilization of memory slots and increased hardware costs with the addition of multiplexers.
Innovation Solution
The motherboard design includes slot groups with first and second memory slots, each with distinct access addresses formed by different voltage levels, and an interface controller that transmits pin control signals to ensure unique access addresses for each slot group, allowing full utilization of memory slots without a multiplexer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional motherboards use fixed connection pin logic levels for memory slots, then address conflicts are avoided for the first four slots, but memory slots beyond four cannot be fully utilized due to repeated access addresses
Solution Approach 1:
The patent applies dynamics by making the connection pin logic levels changeable through control signals. The interface controller dynamically adjusts the logic levels of connection pins SA0-SA2 based on which memory slot group is being accessed, allowing the same physical pins to generate different address values at different times. This resolves the contradiction by enabling full utilization of all memory slots while maintaining unique access addresses through time-dependent dynamic control.
Solution Approach 2:
The patent changes the parameter of connection pin logic levels from fixed to variable. By controlling the logic levels of connection pins SA0-SA2 to be changeable according to the accessed memory slot group, the system can generate distinct access addresses for each slot. This parameter change enables the interface controller to differentiate between multiple memory slots that would otherwise have identical address assignments.
2Adaptability or versatility
If a multiplexer is added to enable access to more than four memory slots, then memory slot utilization improves, but hardware cost and device complexity increase
Solution Approach 1:
The patent applies self-service by using the existing interface controller to generate control signals that directly manage the logic levels of connection pins. The interface controller itself performs the addressing function without requiring external multiplexing hardware. This eliminates the need for additional multiplexers while still enabling access to multiple memory slot groups, thereby reducing hardware complexity and cost.
Solution Approach 2:
The patent makes the interface controller multi-functional by having it perform both the normal interface control function and the additional function of dynamically controlling connection pin logic levels for address generation. This universal approach allows the existing controller to handle multiple memory slot groups without requiring separate multiplexing hardware, thus avoiding increased device complexity.
3Adaptability or versatility
If connection pins SA2 of memory slots are electrically connected with ground voltage to support four addresses, then memory modules with four-address SPD can be used, but access addresses become repeated when more than four memory modules are inserted
Solution Approach 1:
The patent makes the connection pin logic levels dynamic rather than fixed at ground voltage. The interface controller dynamically adjusts the logic levels of connection pins SA0-SA2 based on the currently accessed memory slot group, enabling the system to generate unique access addresses for each slot even though the physical connection pins remain the same. This dynamic control prevents address repetition while maintaining compatibility with four-address SPD memory modules.
Solution Approach 2:
The patent applies preliminary action by pre-defining different logic level combinations for different memory slot groups. Before accessing a specific memory slot, the interface controller sets the appropriate logic levels for the connection pins corresponding to that slot group. This preliminary configuration ensures that each memory slot has a unique address assignment before access occurs, preventing address conflicts.
Data Source
AI summary
The invention provides a motherboard and an interface control method of a memory slot thereof. The motherboard includes a plurality of slot groups, a bus, and an interface controller. Each of the slot groups includes a first memory slot and a second memory slot connected with the bus. The first memory slot and the second memory slot form two different access addresses. The interface controller transmits a plurality of pin control signals to the corresponding slot groups to make the two access addresses of the first memory slot and the second memory slot of a using slot group of the slot groups different from the two access addresses of the first memory slot and the second memory slot of each of the other slot groups. Then, the interface controller accesses the using slot group via the bus.