Store Replay Policy for Cache Line Contention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing processing devices face inefficiencies and high power consumption when committing cacheable stores due to contention and live-lock states, as well as cache lines being repeatedly acquired by different processor cores, leading to poor performance in acquiring and committing cache lines.
Innovation Solution
Implementing a cacheable store replay policy that determines whether to replay a store instruction based on the status of the cache line and execution phase, allowing for efficient re-acquisition of cache lines through a store queue that tracks states and attributes, and performs replays until the cache line is in a writable state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cacheable stores are committed by waiting for the store to become the oldest in the system, then system contention is reduced, but performance deteriorates due to poor efficiency and inefficient power utilization
Solution Approach 1:
The patent implements a dynamic replay policy that adapts the commit timing of cacheable stores based on real-time system conditions. Instead of statically waiting for the oldest store position, the system dynamically determines whether to replay a store instruction based on the status of cache lines and execution phase, optimizing both stability and performance
Solution Approach 2:
The patent introduces feedback mechanisms through store queues that track the state of store instructions and cache lines. The system continuously monitors cache line status and execution phase information, using this feedback to intelligently decide when to replay store instructions, thereby resolving the contradiction between system stability and performance
2Loss of information
If cache lines are repeatedly acquired by different processor cores, then system-wide data visibility is improved, but power consumption increases and performance deteriorates
Solution Approach 1:
The patent applies local quality by implementing store queues at each processor core that locally track and manage cacheable store states. This localized management allows each core to independently optimize its store commit behavior based on local cache line status, reducing unnecessary cross-core traffic and associated power consumption while maintaining data visibility
Solution Approach 2:
The patent performs preliminary actions by pre-tracking the state of cache lines and execution phases in store queues before actual commit operations. This advance preparation allows the system to optimize commit timing and reduce redundant acquisitions, thereby lowering power consumption while ensuring proper data visibility
3Reliability
If cacheable stores are committed after retirement with counter-based attempts, then system contention is managed, but performance and power efficiency remain poor
Solution Approach 1:
The patent replaces simple counter-based mechanisms with intelligent feedback-driven replay policies. The store queues continuously monitor cache line status and execution phase information, using this feedback to make informed decisions about when to replay store instructions, thereby improving performance while maintaining contention management
Solution Approach 2:
The patent implements self-service through store queues that autonomously manage the replay of store instructions based on their own tracked state information. The system serves itself by using internally maintained cache line status and execution phase data to determine optimal commit timing, eliminating the need for external control mechanisms
Data Source
Figure 1
Figure 2~4
Figure 5
AI summary
A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines (130) based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) (135) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.