L2 Cache Duplicate Request Filtering Mechanism
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Solution Overview
Problem
In processors without secondary miss detection in the L1 cache, there is an increased load and power consumption on the L2 cache due to duplicate requests, which complicates hardware and timing requirements and reduces processor performance.
Innovation Solution
The L2 cache filters duplicate requests by storing identifying information and reusing cache line data from a fill buffer to send subsequent load fill packets without additional cache array look-ups, using a pending-access status-holding register (PASHR) to track requests and manage duplicate requests efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If secondary miss detection logic is provided in the L1 cache, then duplicate requests to the L2 cache are prevented, but hardware complexity and timing requirements increase substantially
Solution Approach 1:
The patent extracts the duplicate request detection functionality from the L1 cache and relocates it to the L2 cache. Specifically, the L2 cache implements a filter mechanism that intercepts and examines requests before they are fully processed, identifying duplicate requests at the L2 level rather than requiring secondary miss detection logic in the L1 cache. This extraction resolves the contradiction by maintaining energy efficiency through duplicate request prevention while eliminating the hardware complexity and timing constraints associated with implementing such logic in the L1 cache.
2Productivity
If secondary miss detection logic is provided in the L1 cache, then duplicate requests are filtered, but area and timing cost increase substantially
Solution Approach 1:
The patent introduces an intermediary filtering mechanism at the L2 cache that acts as a mediator between the L1 cache and the rest of the memory subsystem. This intermediary filter examines incoming requests, identifies duplicates using a compact data structure, and prevents them from proceeding further without requiring complex logic in the L1 cache. The intermediary approach maintains high processor performance by filtering duplicates effectively while avoiding the area and timing costs of implementing secondary miss detection in the L1 cache.
3Device complexity
If secondary miss detection is not provided, then hardware is simplified, but duplicate request traffic to the L2 cache increases substantially
Solution Approach 1:
The patent inverts the traditional approach by implementing duplicate request detection at the L2 cache level rather than at the L1 cache level. Instead of having the L1 cache identify and filter duplicates before sending requests to the L2 cache, the system allows all requests to reach the L2 cache and then filters duplicates there. This inversion resolves the contradiction by maintaining hardware simplicity in the L1 cache while still reducing duplicate request traffic and cache load at the L2 level through the implemented filter mechanism.
Data Source
AI summary
The disclosed embodiments provide a system that filters duplicate requests from an L1 cache for a cache line. During operation, the system receives at an L2 cache a first request and a second request for the same cache line, and stores identifying information for these requests. The system then performs a cache array look-up for the first request that, in the process of creating a load fill packet for the first request, loads the cache line into a fill buffer. After sending the load fill packet for the first request to the L1 cache, the system uses the cache line data still stored in the fill buffer and stored identifying information for the second fill request to send a subsequent load fill packet for the second request to the L1 cache without performing an additional cache array look-up.