Ladder-Shaped Gate Line Segmentation for Display Signal Resistance
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Solution Overview
Problem
The increasing number of wiring lines in display devices, such as liquid crystal and organic electroluminescence displays, leads to shorter signal write-in times and higher electric resistance, causing degradation in display quality due to the need to write signals quickly through high-resistance lines.
Innovation Solution
The display device employs a ladder-shaped gate line configuration with distinct portions and connection portions between source lines, reducing the overall resistance of the gate lines without increasing their width, thereby maintaining display quality even at high driving frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of wiring lines is increased to achieve high definition, then the display resolution is improved, but the electric resistance of the wiring lines increases and the signal write-in time decreases
Solution Approach 1:
The gate line is divided into multiple segments (first gate line portion, second gate line portion, third gate line portion) connected in series. Each segment can be independently optimized for resistance characteristics, allowing the overall gate line to maintain low resistance while spanning the required display width. This segmentation resolves the contradiction by enabling high resolution (more gate lines) while maintaining signal transmission quality through optimized segment resistance values.
Solution Approach 2:
Different portions of the gate line are assigned different resistance characteristics. The first gate line portion has higher resistance than the third gate line portion, with the second gate line portion having intermediate resistance. This local quality variation allows each segment to be optimized for its specific position and function, resolving the contradiction between high resolution and signal transmission quality by ensuring that no single segment has excessively high resistance.
2Area of stationary object
If the width of the wiring lines is reduced to maintain aperture ratio, then the aperture ratio is maintained, but the electric resistance of the wiring lines increases
Solution Approach 1:
The gate line is divided into multiple segments with different width characteristics. By segmenting the gate line, the patent enables different width optimizations in different portions - narrower segments where space is constrained and wider segments where resistance reduction is prioritized. This resolves the contradiction between maintaining aperture ratio (narrower lines) and maintaining signal transmission quality (wider lines for lower resistance).
Solution Approach 2:
Different portions of the gate line structure have different local qualities - specifically, different widths and resistance values. The first gate line portion has different width characteristics than the third gate line portion, allowing each local region to be optimized for its specific requirements. This local quality approach resolves the contradiction by ensuring that aperture ratio is maintained in critical areas while resistance is reduced in areas where signal transmission is most sensitive.
3Speed
If the signal write-in time is shortened to achieve high driving frequency, then the driving frequency is improved, but the signal transmission quality degrades due to high resistance
Solution Approach 1:
The gate line is segmented into multiple portions with optimized resistance characteristics, allowing faster signal propagation across the entire gate line length. By reducing the resistance of individual segments (particularly the third gate line portion which has the lowest resistance), the overall signal write-in time is reduced, enabling higher driving frequencies while maintaining signal transmission quality.
Solution Approach 2:
Different portions of the gate line have different resistance values optimized for their specific functions. The third gate line portion has the lowest resistance to enable rapid signal write-in, while the first gate line portion has higher resistance. This local quality differentiation resolves the contradiction between high driving frequency (requiring fast signal write-in) and signal transmission quality by ensuring that critical signal paths have appropriately low resistance.
Data Source
AI summary
According to one embodiment, a display device includes first and second source lines arranged along a first direction, a gate line including first and second portions arranged along a second direction intersecting the first direction, and a connection portion which connects the first portion and the second portion to each other and a semiconductor layer which intersects at least one of the first portion and the connection portion, and each of the first portion and the second portion intersects the first and second source lines and the connection portion is located between the first source line and the second source line.