Laminate Insert Package Embedding Semiconductor Chips
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Solution Overview
Problem
Existing methods for embedding semiconductor components into substrates, such as printed circuit boards, face challenges in minimizing device size, weight, and production costs while maintaining efficient electrical connections and versatility in circuit design.
Innovation Solution
The development of a laminate insert package that embeds semiconductor chips between metal foils, using a lamination process to create a sandwich structure with electrical connections, allowing for the integration of multiple chips and passives within a layer stack substrate, enabling efficient electrical contact through global vias and enhancing circuit functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are directly embedded into substrates using conventional methods, then electrical connections can be established, but device size and weight cannot be minimized effectively
Solution Approach 1:
The patent embeds complete laminate structures containing semiconductor chips, metal foils, and electrical connections within one another, creating a nested configuration where multiple functional layers are integrated into a compact three-dimensional arrangement that minimizes overall device volume
Solution Approach 2:
The patent combines multiple discrete components (semiconductor chips, metal foils, electrical connections, and substrate layers) into a single integrated laminate insert package, merging these elements into one cohesive structure that reduces total device size and simplifies the embedding process
2Productivity
If conventional embedding methods are used, then semiconductor components can be integrated, but production costs increase
Solution Approach 1:
The patent prepares complete laminate insert packages with pre-formed electrical connections, metal foils, and semiconductor chip integrations before final substrate assembly, allowing these components to be manufactured and tested separately under optimized conditions that reduce overall production costs
Solution Approach 2:
The patent divides the final device into modular laminate insert packages that can be manufactured independently and then integrated into the substrate, enabling parallel production processes and reducing manufacturing complexity and costs
3Volume of moving object
If device size is reduced through embedding, then compactness is achieved, but electrical connection efficiency may deteriorate
Solution Approach 1:
The patent transitions from planar electrical connections to three-dimensional vertical connections using metal foils and global vias that extend through multiple laminate layers, enabling efficient electrical pathways that maintain connection reliability while reducing the device's horizontal footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device size and weight, lowers production costs, and provides high versatility in circuit design, enabling the creation of compact electronic devices with enhanced electrical connectivity and functionality.
Implementation Method 1
using a lamination process to create a sandwich structure
Data Source
AI summary
A method of producing a laminate insert package includes providing a first metal layer, printing a first dielectric layer on the first metal layer, providing a second metal layer, printing a second dielectric layer on the second metal layer, and printing a dielectric spacer layer on the first dielectric layer. At least one semiconductor chip is attached to either the first or the second metal layer. A first layer assembly comprising the first metal layer, the first dielectric layer, the dielectric spacer layer and a second layer assembly comprising the second metal layer and the second dielectric layer are brought together. The first and second layer assemblies are laminated to form a laminate insert package, whereby the at least one semiconductor chip is embedded within the laminate insert package.