Laminated Capacitor Stacking for Higher DRAM Capacitance
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) capacitors have a relatively small capacitance value, which limits their charge storage capacity and overall performance.
Innovation Solution
A laminated capacitor structure is developed, comprising a substrate with alternating layers of connection structures and sub-capacitor structures, each consisting of discrete bottom and top electrodes separated by a dielectric medium, where the electrodes are electrically connected through spacers to increase the effective area and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a traditional single-layer capacitor structure is used, then the device complexity is low, but the capacitance value is small
Solution Approach 1:
The patent transitions from a planar single-layer capacitor structure to a three-dimensional laminated structure by stacking multiple sub-capacitor structures vertically. This dimensional change allows the capacitor to achieve significantly higher capacitance values by utilizing vertical space, effectively solving the contradiction between maintaining simple structure and increasing capacitance.
Solution Approach 2:
The capacitor is divided into multiple discrete sub-capacitor structures (first sub-capacitor structure, second sub-capacitor structure, etc.), each with its own electrodes and dielectric layers. These segmented units are stacked and connected through conductive spacers, allowing the total capacitance to be the sum of individual sub-capacitor capacitances while maintaining modular simplicity in the manufacturing process.
2Quantity of substance
If the capacitance value is increased, then the charge storage capacity is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs preliminary patterning actions where conductive spacers are formed before final electrode connections. The spacers are pre-positioned between sub-capacitor structures to establish electrical connections, and subsequent steps fill and planarize the structure. This preliminary arrangement simplifies the overall manufacturing by establishing the vertical connection architecture early in the process.
Solution Approach 2:
The manufacturing process uses nested fabrication steps where conductive materials are deposited and patterned within previously formed structures. For example, bottom electrodes of upper sub-capacitors are formed within the vertical space defined by lower sub-capacitor structures and their associated spacers, creating a nested assembly that increases charge storage capacity while following a systematic manufacturing sequence.
Data Source
AI summary
A laminated capacitor and a method for manufacturing the same are provided. The method includes operations of providing a substrate; forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads on the substrate; forming a sub-capacitor structure on the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and repeatedly performing an operation of forming a connection structure and the sub-capacitor structure for N times on the sub-capacitor structure, such that N connection structures and N+1 sub-capacitor structures are alternately arranged along a direction perpendicular to the substrate, wherein N is an integer greater than or equal to 1.