Laminated Capacitor Wiring Structure for High-Frequency Decoupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional surface-mounted decoupling capacitors are ineffective at high frequencies due to high parasitic inductance, while embedded laminated capacitors also face parasitic inductance issues, limiting their ability to stabilize voltage fluctuations in modern high-speed circuit designs.
Innovation Solution
A laminated capacitor wiring structure with a supplemental via placed between the power and ground vias, reducing the length of the current loop and thereby decreasing parasitic inductance, is introduced. This structure includes conductive layers and dielectric layers, with the supplemental via being shorter than the power and ground vias, allowing for a more efficient current path and reduced parasitic inductance effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If surface-mounted decoupling capacitors are used, then ease of manufacture is improved, but parasitic inductance increases and high frequency performance deteriorates
Solution Approach 1:
The patent transitions from surface-mounted capacitors to laminated capacitors embedded within the PCB structure. This dimensional change allows the capacitor to be integrated into the board's internal layers, significantly reducing the distance between the capacitor and IC power supply connections, thereby reducing parasitic inductance while maintaining ease of manufacture through automated lamination processes.
Solution Approach 2:
The laminated capacitor is nested within the PCB structure, with conductive layers and dielectric layers integrated into the board's internal architecture. The capacitor elements are embedded between PCB layers, allowing the capacitor to be part of the board structure itself rather than a separate surface-mounted component, reducing parasitic inductance and improving high frequency performance.
2Area of stationary object
If laminated capacitors are embedded in circuit board, then surface area occupation is reduced, but parasitic inductance from power and ground vias increases
Solution Approach 1:
The patent segments the current path by introducing multiple power vias and ground vias distributed across different conductive layers. This segmentation divides the single long current loop into multiple shorter paths, reducing the overall parasitic inductance. The current can flow through multiple parallel via paths rather than a single series path, effectively lowering the equivalent inductance.
Solution Approach 2:
The patent utilizes the third dimension (vertical depth) by distributing vias across multiple PCB layers. Instead of using a single plane for power and ground connections, the invention creates a three-dimensional via structure where power and ground connections are distributed across different layers, reducing the effective current loop area and parasitic inductance while maintaining compact surface area usage.
3Reliability
If power and ground vias are used in laminated capacitors, then electrical connection is achieved, but parasitic inductance increases at high frequencies
Solution Approach 1:
The patent segments the via structure into multiple shorter via paths distributed across different conductive layers. Instead of using single long vias that extend through the entire PCB thickness, the invention uses multiple shorter vias connected through intermediate conductive layers, reducing the effective via length and associated parasitic inductance while maintaining reliable electrical connection.
Solution Approach 2:
The patent employs multiple power vias and ground vias in parallel, using excessive via count to reduce individual via current density and parasitic inductance. By providing multiple parallel paths for current flow, the overall equivalent inductance is reduced, and the electrical connection reliability is enhanced through redundancy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively decreases parasitic inductance and impedance, enhancing the decoupling effect and bypass bandwidth at high frequencies, making it suitable for high-speed circuit applications.
Implementation Method 1
parasitic inductance caused by the internal wirings
Implementation Method 2
impedance from the power and ground vias
Data Source
AI summary
The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.