Laminated Gate Electrodes for TFT Manufacturing
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Solution Overview
Problem
The conventional polycrystalline silicon TFT manufacturing process requires a high number of photolithography processes to produce n-channel and p-channel TFTs separately, leading to reduced throughput and increased costs.
Innovation Solution
The image display device employs a matrix configuration of gate lines and signal lines on an insulating substrate with laminated electrodes, where gate electrodes of one type are of the same material as pixel electrodes, and gate electrodes of the other type have a laminated structure matching the gate lines and pixel electrodes, reducing the number of photolithography processes needed for ion implantation and threshold adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate manufacturing processes are used for n-channel and p-channel TFTs, then manufacturing precision can be maintained, but productivity decreases due to increased number of photolithography processes
Solution Approach 1:
The patent combines the manufacturing processes for n-channel and p-channel TFTs into a unified flow. By forming gate electrodes and performing ion implantation in an integrated sequence rather than separately processing each transistor type, the number of photolithography steps is reduced while maintaining precise threshold value control through selective ion implantation regions.
Solution Approach 2:
The patent creates a universal manufacturing process that handles both n-channel and p-channel TFTs through the same gate electrode formation and ion implantation steps. The process uses material selection and ion implantation parameters to differentiate between transistor types, eliminating the need for separate dedicated process lines while preserving manufacturing precision.
2Manufacturing precision
If multiple photolithography processes are performed for ion implantation and threshold adjustment, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary gate electrode formation and material deposition before ion implantation steps. By preparing the gate electrode structure in advance with appropriate materials and layers, the subsequent ion implantation can be performed more efficiently with fewer preparatory photolithography steps, reducing overall process time while maintaining threshold adjustment precision.
Solution Approach 2:
The patent establishes a continuous manufacturing flow where gate electrode formation, ion implantation, and threshold adjustment occur in an integrated sequence without interruption. The process eliminates idle time between separate n-channel and p-channel TFT manufacturing cycles, maintaining continuous production while achieving precise threshold values through controlled ion implantation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the number of photolithography processes, enhancing manufacturing throughput and reducing costs while maintaining high-resolution image display capabilities for liquid crystal, OLED, and other active matrix-type image display devices.
Implementation Method 1
The amorphous silicon layer is then crystallized by irradiation with a XeCl excimer laser beam
Implementation Method 2
The amorphous silicon layer is then crystallized by irradiation with a XeCl excimer laser beam, and an island-like polycrystalline silicon layer PSI is obtained
Implementation Method 3
phosphorus ions are then implanted to adjust the threshold value of the p-channel TFT
Data Source
AI summary
An image display device of reduced cost is provided. A plurality of gate lines, a plurality of signal lines formed to cross the gate lines in a matrix fashion, and a plurality of thin-film transistors are formed on an insulating substrate, and the plurality of gate lines are laminated electrodes. The plurality of thin-film transistors are configured of transistors of two types of an n-channel conductivity type and a p-channel conductivity type. Gate electrodes of thin-film transistors of one type are laminated electrodes of the same configuration as the gate lines, and gate electrodes of thin-film transistors of the other type are configured of electrodes of the same layer as bottom electrodes of the gate lines.