Land-Side Silicon Capacitor Layout for Lower ESL and ESR
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Solution Overview
Problem
Conventional semiconductor packaging faces challenges with power supply noise due to high current density and voltage drops, which are exacerbated by the limitations of multi-layer ceramic capacitors (MLCC) in regulating current flow and reducing electromagnetic interference.
Innovation Solution
A land-side silicon capacitor design comprising two silicon capacitor unit dies adjoined with an integral scribe line region, surrounded by a die seal ring, and connected in parallel through a package substrate, which reduces effective series inductance and resistance while increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-layer ceramic capacitors (MLCC) are used to regulate current flow and prevent electromagnetic interference, then power supply noise is reduced, but the effectiveness is limited by parasitic elements including equivalent series inductance (ESL) and equivalent series resistance (ESR)
Solution Approach 1:
The patent changes the physical and electrical parameters of the capacitor by using silicon-based materials with different dielectric properties compared to conventional MLCC. The silicon capacitor structure achieves lower ESL and ESR values by modifying the capacitor's construction parameters including the use of silicon dioxide as dielectric material and specific electrode configurations, thereby reducing parasitic effects while maintaining noise filtering capability
Solution Approach 2:
The invention employs composite material structures combining silicon substrate, silicon dioxide dielectric layers, and conductive electrodes to create a capacitor with superior electrical characteristics. This composite approach allows optimization of each layer's properties to minimize parasitic inductance and resistance while maximizing capacitance, directly addressing the limitation of conventional MLCC parasitic elements
2Use of energy by moving object
If on-chip transistors are scaled down to operate at lower power supply voltages, then power consumption is reduced, but voltage drop increases affecting circuit operation
Solution Approach 1:
The silicon capacitor is strategically positioned on the package substrate near the semiconductor die to provide preliminary charge storage and voltage stabilization. This preliminary action ensures that voltage fluctuations are compensated before they affect the scaled-down transistors, maintaining voltage stability despite the lower operating voltages enabled by power scaling
Solution Approach 2:
The capacitor acts as an intermediary energy storage element between the power supply and the scaled-down transistors. It mediates the voltage fluctuations caused by high current density in miniaturized transistors by charging and discharging as needed, thereby stabilizing the power supply voltage and ensuring reliable operation of low-voltage circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively mitigates power supply noise and electromagnetic interference, enhancing the stability and efficiency of current supply to high-speed applications by providing lower ESL and ESR and higher capacitance.
Implementation Method 1
MLCC works as a 'dam' that temporarily charges and discharges electricity, which regulates the current flow in a circuit
Implementation Method 2
Because thickness of single dielectric and number of stacked layers are related with capacity of electricity
Data Source
AI summary
A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.