Laser-Ablated Embedded Circuit Pattern Fabrication

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Solution Overview

Problem

The existing over-plate and over-etch processes for forming circuit patterns are slow and costly, leading to inefficiencies and potential shorts in circuit formation.

Innovation Solution

A method involving the formation of laser-ablated artifacts through a resist and conductive layer into a dielectric layer, followed by filling and selectively removing conductive layers to create an embedded circuit pattern without the need for over-plate and over-etch processes, resulting in a dimple-free pattern.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If over-plate and over-etch processes are used to form circuit patterns, then complete filling and short prevention are achieved, but fabrication time and cost increase significantly

Engineering Contradiction:
Improvecircuit pattern qualityVSAvoidfabrication speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by forming a mandrel structure with precise dimensions before copper deposition. The mandrel is designed with specific height and width parameters that pre-determine the final copper fill dimensions, eliminating the need for subsequent over-etching to remove excess copper. This preliminary structuring ensures complete feature filling while maintaining precise dimensional control.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical/chemical over-etch process with a controlled deposition approach. Instead of using etching chemistry to remove excess copper, the method uses physical mandrel structures and controlled copper deposition to achieve precise fill levels, substituting a mechanical positioning system for a chemical removal system.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If over-plate process is used to ensure complete feature filling, then dimple formation is prevented, but process complexity and cost increase

Engineering Contradiction:
Improvefeature filling completenessVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts the critical dimensional control function from the copper deposition process itself and places it in the mandrel structure. By removing the need for over-plating and subsequent over-etching, the method eliminates redundant process steps while maintaining complete feature filling through the mandrel's physical constraints.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the approach from controlling copper fill through deposition parameters (over-plate) and removal parameters (over-etch) to controlling fill through mandrel geometric parameters (height, width, shape). This parameter transformation simplifies the process by using physical dimensions rather than chemical/process parameters.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for the rapid and cost-effective fabrication of dimple-free embedded circuit patterns, eliminating the need for time-consuming and costly over-plate and over-etch processes.

Implementation Method 1

forming laser-ablated artifacts through the first resist layer, through the first conductive layer, and at least partially into the dielectric layer

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS7752752B1Method of fabricating an embedded circuit pattern
Publication Date: 2010.07.13 AMKOR TECH SINGAPORE HLDG PTE LTD
  • US7752752B1 patent drawing
  • US7752752B1 patent drawing
  • US7752752B1 patent drawing

AI summary

A method of fabricating a substrate includes forming a first conductive layer on a dielectric layer, forming a resist layer on the first conductive layer, and forming laser-ablated artifacts through the first resist layer, through the first conductive layer, and at least partially into the dielectric layer. A second conductive layer is formed within the laser-ablated artifacts. The laser-ablated artifacts are filled to form an overfilled circuit pattern. The resist layer and the first conductive layer are removed. Further, a portion of the overfilled circuit pattern is removed to form an embedded circuit pattern embedded within the dielectric layer.