3D Transistor Stacking via Laser Annealing of Polysilicon
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistors beyond two-dimensional (2D) circuits, as they struggle to achieve high-density three-dimensional (3D) integration for logic chips, with existing methods like wafer bonding being inefficient for creating multiple layers of defect-free silicon with preferred crystal orientations.
Innovation Solution
The method involves forming multiple planes of transistors by converting polycrystalline silicon to single-crystal silicon using laser annealing and metal-induced crystallization, allowing for the creation of multiple single-crystal silicon layers with specific orientations, which enables the formation of high-density 3D integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafer bonding is used for 3D integration, then device stacking is achieved, but manufacturing complexity and difficulty of creating defect-free silicon layers increase
Solution Approach 1:
The patent transitions from traditional 2D planar transistor fabrication to 3D vertical stacking by forming multiple silicon layers with different crystal orientations. This dimensional change allows transistors to be stacked vertically, dramatically increasing transistor density while maintaining manufacturability through a systematic multi-layer formation process.
Solution Approach 2:
The invention divides the silicon structure into multiple discrete layers with different crystal orientations (e.g., <100>, <110>, <111>). Each layer can be independently formed and controlled, allowing complex 3D structures to be built from simpler segmented components, thereby reducing overall manufacturing complexity.
2Reliability
If multiple silicon layers with preferred crystal orientations are created, then transistor performance and signal propagation improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent systematically varies the crystal orientation parameter of silicon layers (e.g., <100>, <110>, <111> orientations) to optimize transistor performance and signal propagation. By controlling this fundamental material parameter, the invention achieves improved reliability while maintaining manageable manufacturing precision through established semiconductor fabrication techniques.
3Manufacturing precision
If polycrystalline silicon is converted to single crystal silicon, then material quality and device performance improve, but processing time and energy consumption increase
Solution Approach 1:
The patent replaces traditional thermal annealing processes with laser-induced crystallization to convert polycrystalline silicon to single crystal silicon. This substitution of the crystallization mechanism dramatically reduces processing time and energy consumption while maintaining high crystal quality, as the laser process is faster and more localized than conventional thermal methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of more than 20 layers of high-quality single-crystal silicon planes, enhancing transistor density and enabling efficient 3D logic and memory formation, improving signal propagation and reducing manufacturing costs.
Implementation Method 1
annealing the first layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon
Implementation Method 2
making upper silicon planes to be a preferred crystal orientation
Data Source
AI summary
A method of forming transistor devices includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of field effect transistors; depositing a first insulator layer on the first transistor plane; forming holes in the first insulator layer using a first etch mask; depositing a first layer of polycrystalline silicon on the first insulator layer, the first layer of polycrystalline filling the holes and covering the first insulator layer; and annealing the first layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon. A top surface of the first transistor plane is a top surface of a stack of silicon formed by epitaxial growth.