Latch-Based Power Glitch Detection for Security Chips
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Solution Overview
Problem
Existing power glitch signal detection circuits in security chips suffer from high chip area overhead, low reaction rate, low sensitivity, and high static power consumption, making them vulnerable to fault attacks and ineffective in detecting nanosecond-level glitches.
Innovation Solution
A power glitch signal detection circuit utilizing a latch structure without resistors, which reduces hardware overhead, enhances detection speed, and eliminates static bias current, allowing for low power consumption, small area, high sensitivity, and strong portability, while using a latch-capacitor configuration to detect glitches with lower amplitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If RC sampling structure with larger RC is used to detect nanosecond-level power glitch, then detection sensitivity is improved, but chip area overhead increases
Solution Approach 1:
The patent extracts and removes the resistor component from the traditional RC sampling structure, creating a capacitor-only sampling circuit. This eliminates the need for resistor area while maintaining the voltage sampling function through capacitive coupling, directly resolving the contradiction between detection sensitivity and chip area overhead.
Solution Approach 2:
The patent replaces the resistive element with a capacitive element in the sampling circuit, substituting the RC time constant mechanism with a capacitive voltage division mechanism. This substitution maintains the nanosecond-level glitch detection capability while eliminating the area overhead associated with resistors.
2Measurement precision
If comparator structure with decision threshold is used to detect power glitch, then detection accuracy is improved, but static bias power consumption increases
Solution Approach 1:
The patent extracts and removes the comparator component from the detection circuit, replacing it with a latch-based detection mechanism. This elimination of the comparator structure directly eliminates the static bias current and associated power consumption while maintaining detection accuracy through the latch's threshold-based triggering mechanism.
Solution Approach 2:
The patent employs a latch structure that operates in a pulsed manner rather than continuously. The latch is triggered temporarily by the glitch signal and then resets, consuming power only during the detection event rather than maintaining continuous static bias current, effectively reducing power consumption while preserving detection accuracy.
3Reliability
If traditional power glitch detection circuit is used, then basic detection function is provided, but reaction rate is low
Solution Approach 1:
The patent employs a periodic triggering mechanism where the latch is reset after each detection event, allowing the circuit to be ready for the next glitch detection. This periodic reset and trigger operation enables the circuit to maintain high reaction rate for sequential glitch detections while preserving reliable detection function.
Solution Approach 2:
The patent uses a direct capacitive coupling path from the power supply node to the latch input, allowing the glitch signal to rush through the circuit without delay. This direct path eliminates intermediate processing stages, enabling nanosecond-level response time and high reaction rate while maintaining detection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively detects power glitches with improved sensitivity and reduced power consumption, enhancing the robustness and safety of security chips against fault attacks by quickly identifying voltage fluctuations.
Implementation Method 1
a capacitor is configured to couple a power supply voltage to an input of the latch
Data Source
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AI summary
A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit comprises: a latch and a signal output module, wherein a first input of the latch is connected to a power supply voltage, a first output of the latch is connected to a ground voltage, a second input of the latch is connected to a third output of the latch, a third input of the latch is connected to a second output of the latch, and the second output or the third output is connected to the signal output module. The power glitch signal detection circuit could detect a power glitch on the power supply voltage or the ground voltage, and the power glitch signal detection circuit has the advantages of low power consumption, small area, high speed, high sensitivity and strong portability.