Latch-Type Sense Amplifier Integration for Compact Scan Testing

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Solution Overview

Problem

Conventional scan techniques for integrated circuit testing require significant memory and test time, and result in large vector sets due to the need for additional shadow latch circuits and complex logic circuits.

Innovation Solution

A sense amplifier cooperates with a data output latch circuit to generate test results in test mode, eliminating the need for additional shadow latch circuits and optimizing area and power consumption by integrating a sense amplifier and data output latch circuit within the DFT circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional scan techniques are used for integrated circuit testing, then testing functionality is achieved, but area and power consumption increase due to additional shadow latch circuits and complex logic circuits

Engineering Contradiction:

Improvetesting functionalityVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the sense amplifier with the data output latch circuit to form an integrated test circuit. The sense amplifier's latch circuit is combined with the data output latch circuit, eliminating the need for separate shadow latch circuits. This integration maintains testing functionality while reducing the overall circuit area by removing redundant components.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated sense amplifier and data output latch circuit serves multiple functions: it performs both data output operations during normal mode and testing operations during test mode. The circuit can function as a sense amplifier for reading data and as a latch circuit for capturing test data, eliminating the need for dedicated shadow latch circuits for testing.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If conventional scan techniques are used for integrated circuit testing, then testing functionality is achieved, but power consumption increases due to additional shadow latch circuits and complex logic circuits

Engineering Contradiction:

Improvetesting functionalityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If conventional scan techniques are used for integrated circuit testing, then testing functionality is achieved, but test time increases due to large vector sets

Engineering Contradiction:

Improvetesting functionalityVSAvoidtest time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and eliminates the shadow latch circuits from the conventional scan testing architecture. By removing these redundant circuits, the patent reduces the complexity of the test vector sets required, thereby reducing the time needed to complete testing operations while maintaining full testing functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

4Reliability

If additional shadow latch circuits are added for scan testing, then testing functionality is improved, but area and power consumption increase

Engineering Contradiction:

Improvetesting functionalityVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12400723B2Latch type sense amplifier for testing

Publication Date: 2025.08.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device is provided and includes a sense amplifier and an output latch circuit. The sense amplifier adjusts voltage levels of first and second data lines according to a bypass data signal corresponding to a data signal in response to a first enable signal having a first logic state and a second enable signal having a second logic state different from the first logic state during a test mode. The output latch circuit generates a data output signal according to the voltage level of the first data line in response to the first enable signal having the second logic state and a third enable signal having the first logic state during the test mode.