Lateral Die Stacking With Vertical Bridge Chip Interconnect
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Solution Overview
Problem
Existing packaging technologies for semiconductor devices, such as through silicon via (TSV) and silicon interposers, face challenges including increased space consumption, parasitic capacitance, and higher power consumption due to the use of discrete bridge dies, which complicate 3D stacking and limit scalability and performance.
Innovation Solution
The method involves positioning a third silicon chip vertically between two horizontally positioned silicon chips and electrically connecting them using through silicon vias (TSVs) or hybrid bonding, eliminating the need for discrete bridge dies, thereby simplifying 3D stacking and reducing the number of stacked dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete bridge dies are used to connect silicon chips, then electrical connection between chips is achieved, but space consumption increases and device complexity increases
Solution Approach 1:
The patent merges the functions of multiple discrete bridge dies into a single integrated silicon chip structure. The new design integrates interconnect pathways and logic functions directly into the chip substrate, eliminating the need for separate bridge die components while maintaining electrical connection capabilities between stacked chips.
Solution Approach 2:
The integrated silicon chip structure serves multiple functions simultaneously: it provides mechanical support, electrical interconnection, and logic processing capabilities. The chip substrate is designed to host both interconnect pathways and functional logic, making it a universal component that replaces specialized bridge die while adding computational value.
2Adaptability or versatility
If discrete bridge dies are used for die-to-die interconnect, then high interconnect density is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines interconnect formation and logic fabrication into a single manufacturing process flow. By integrating these functions into one chip structure, the complex multi-step process of assembling separate bridge die is replaced with standard semiconductor manufacturing techniques, reducing both complexity and cost.
3Reliability
If traditional 3D stacking with bridge die is used, then chip connectivity is achieved, but the number of stacked dies increases and scalability is limited
Solution Approach 1:
The patent merges multiple functional layers into a reduced number of stacked chips. By integrating interconnect and logic functions into the chip substrate itself, the system achieves the same connectivity with fewer discrete components, improving scalability and reducing stacking complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces space consumption, lowers power consumption, and enhances performance by enabling a highly scalable topology with a wide range of die counts, while simplifying 3D stacking and reducing costs.
Implementation Method 1
electrically connecting them using through silicon vias (TSVs)
Implementation Method 2
electrically connecting them using through silicon vias (TSVs) or hybrid bonding
Data Source
AI summary
Disclosed methods for lateral stacking of die can include positioning a first silicon chip of a semiconductor device horizontally with respect to a second silicon chip of the semiconductor device. The methods can additionally include positioning a third silicon chip of the semiconductor device vertically with respect to both the first silicon chip and the second silicon chip. The disclosed methods can also include electrically connecting the first silicon chip and the second silicon chip by the third silicon chip. Various other methods and systems are also disclosed.