Lateral IGBT Segmented Junctions for On-Resistance and Switching Speed

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Solution Overview

Problem

Lateral Insulated-Gate Bipolar Transistors (LIGBTs) face challenges in achieving a balance between on-resistance and turning-off time due to residual minority carrier holes, leading to higher power consumption and longer switching times.

Innovation Solution

The LIGBT design incorporates P+ shallow junctions and an N+ shallow junction between the anode and cathode terminals, allowing for efficient hole injection and quick extraction of minority carriers when turned on and off, respectively, by forming multiple injection paths and a low-resistance extraction path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If LIGBT uses conventional structure with P well and N-region, then on-resistance is reduced by carrier injection, but turning-off time increases due to residual minority carrier holes

Engineering Contradiction:
Improveon-resistanceVSAvoidturning-off time
Core Design Contradiction:
Length of stationary objectVSLoss of time

Solution Approach 1:

The P well is divided into multiple P+ shallow junctions (first, second, and third P+ shallow junctions) at different depths and positions. This segmentation creates multiple independent hole injection paths, allowing efficient on-resistance reduction while enabling selective extraction of minority carriers for faster turn-off through the specifically positioned third P+ shallow junction near the drift region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different P+ shallow junctions are positioned at different locations and depths within the P well to perform different functions: the first and second P+ shallow junctions provide general hole injection, while the third P+ shallow junction is specifically positioned near the drift region to facilitate rapid minority carrier extraction during turn-off, creating local quality variations that optimize both on-resistance and turn-off time.

Inventive Principle:
Principle #3Local quality

2Reliability

If LIGBT increases hole concentration to reduce on-resistance, then conductivity improves, but power consumption increases due to residual minority carriers

Engineering Contradiction:
Improveconductive modulation effectVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The segmented P+ shallow junctions create multiple injection paths that optimize hole distribution. The third P+ shallow junction positioned near the drift region enables efficient minority carrier extraction, reducing residual holes and associated power consumption while maintaining the conductive modulation effect through coordinated operation of all P+ shallow junctions during on-state.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces on-resistance and enhances switching speed by enabling efficient hole injection and rapid extraction of minority carriers, thereby minimizing power consumption and turning-off time losses.

Implementation Method 1

an efficient injection of holes can be achieved and the on-resistance can be reduced by a longitudinal injection of the P+ shallow junctions and the P well and a lateral injection of the P+ shallow junctions

Methodology Applied
Scientific EffectCarrier injection:

Implementation Method 2

a path quickly extracting minority carrier (holes) is formed by the N-type buffer region, the N-region and the N+ shallow junctions, which achieves a quick turning-off and reduces a turning-off state loss

Methodology Applied
Scientific EffectMinority carrier extraction:

Data Source

PatentEP3240039B1Lateral insulated-gate bipolar transistor
Publication Date: 2021.07.28 CSMC TECH FAB2 CO LTD
  • EP3240039B1 patent drawingFigure 1~2

AI summary

A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.