Lateral Metal Emitter Interconnect for Transistor Matching

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Solution Overview

Problem

Transistor mismatches in differential, current mirror, and voltage reference circuits lead to errors in output voltage and current magnitudes, particularly exacerbated by thermal cycling, which affects the accuracy and stability of integrated circuits.

Innovation Solution

The placement of metal emitter interconnects is modified to be laterally away from the emitter window, reducing stress on the emitter region and improving transistor matching, thereby minimizing the impact of thermal cycling on input offset voltage and temperature coefficients.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal emitter interconnects are placed over the emitter window, then electrical connection is achieved, but stress on the emitter region increases causing transistor mismatch

Engineering Contradiction:
Improvetransistor matchingVSAvoidstress on emitter region
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The metal emitter interconnect is extracted from its conventional position over the emitter window and relocated to a position lateral to the emitter window. This removes the harmful stress that the metal interconnect imposes on the emitter region while maintaining the necessary electrical connection through alternative routing.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The metal emitter interconnect is repositioned from a vertical arrangement (over the emitter window) to a lateral arrangement (beside the emitter window). This dimensional change in placement allows the interconnect to maintain electrical functionality while eliminating the mechanical stress concentration that caused transistor mismatch during thermal cycling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If conventional transistor layout is used, then manufacturing is simplified, but thermal cycling causes drift in input offset voltage

Engineering Contradiction:
Improveinput offset voltage stabilityVSAvoidtransistor matching stability
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The metal emitter interconnect is pre-positioned lateral to the emitter window during manufacturing, before thermal cycling occurs. This preliminary correct placement prevents the development of stress-induced mismatches that would otherwise occur during subsequent thermal cycling, thereby maintaining input offset voltage stability.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If metal emitter interconnects are placed lateral to emitter window, then stress on emitter region is reduced, but interconnect length increases

Engineering Contradiction:
Improvetransistor matchingVSAvoidinterconnect length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The metal emitter interconnect is positioned specifically in the lateral region adjacent to the emitter window rather than over it. This localized repositioning reduces stress on the critical emitter region while the increased interconnect length is accepted as a necessary trade-off to achieve improved transistor matching and reduced input offset voltage drift.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces the drift in input offset voltage and improves the temperature coefficient stability, resulting in more predictable and accurate transistor performance over multiple thermal cycles.

Implementation Method 1

The placement of metal emitter interconnects is modified to be laterally away from the emitter window, reducing stress on the emitter region

Methodology Applied
Scientific EffectStress Relaxation: Stress Relaxation

Implementation Method 2

improving transistor matching, thereby minimizing the impact of thermal cycling on input offset voltage and temperature coefficients

Methodology Applied
Scientific EffectThermal Expansion: Thermal Expansion

Data Source

PatentUS8339197B2Circuitry including matched transistor pairs
Publication Date: 2012.12.25 NAT SEMICON CORP
  • US8339197B2 patent drawing
  • US8339197B2 patent drawing
  • US8339197B2 patent drawing

AI summary

Matched bipolar transistor pairs for use in differential transistor pair circuitry, current mirror transistor pair circuitry and voltage reference transistor pair circuitry are disclosed. Each transistor in the pair includes a base, emitter and a collector region and a doped polysilicon emitter contact, a metal emitter contact and an metal emitter interconnect which makes an electrical connection to the emitter region by way of the metal emitter contact and the polysilicon emitter contact. The metal emitter interconnect is displaced latterly away from the emitter region so that no part of the metal emitter interconnect overlies any portion of the emitter region.