Lateral Power Transistor Floating Electrode Carrier Control
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Solution Overview
Problem
Lateral Insulated Gate Bipolar Transistors (LIGBTs) face challenges in achieving a balance between on-state and switching losses, with high switching losses due to deep carrier injection into the substrate, which slows down switching speed and contributes to parasitic thyristor activation, especially at high temperatures.
Innovation Solution
The introduction of floating semiconductor regions with higher doping concentrations and a floating electrode above these regions reduces carrier injection into the substrate, lowering the gain of PNP transistors and enhancing turn-off speed by controlling charge injection and recombination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If carrier lifetime is reduced to increase switching speed, then switching speed increases, but on-state voltage drop increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile in the drift layer, with higher doping concentrations near the drain region. This localized modification allows different regions to have different functions: the bulk drift layer maintains low on-state resistance through conductivity modulation, while the drain region provides fast carrier removal through lifetime killing centers.
Solution Approach 2:
The patent changes the physical parameters of the drift layer by introducing lifetime killing centers through specific doping concentrations and implantation energies. This modifies the carrier lifetime parameter locally at the drain region, enabling faster charge removal during turn-off while maintaining low on-state losses through conductivity modulation.
2Power
If deep carrier injection into substrate occurs, then on-state current increases, but switching losses increase and parasitic thyristor activation occurs
Solution Approach 1:
The patent applies preliminary anti-action by pre-introducing lifetime killing centers in the drift layer before operation. These centers are positioned to intercept and recombine carriers before they can reach the substrate and activate parasitic thyristors, while still allowing sufficient current conduction during on-state.
Solution Approach 2:
The patent converts the potentially harmful deep carrier injection into a beneficial effect by using the same carrier flow to activate conductivity modulation in the drift layer, while simultaneously using lifetime killing centers to prevent harmful substrate injection. The harmful carriers are redirected to recombine in the drift layer rather than reaching the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces switching losses and increases turn-off speed while suppressing parasitic thyristor activation, optimizing the trade-off between on-state and switching performance.
Implementation Method 1
The n-type and p-type floating semiconductor regions are configured to remove carriers from the drift region by recombination
Implementation Method 2
a gate placed above and in direct contact to the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region
Implementation Method 3
Electrical conductivity of the drift layer in an IGBT can be sharply increased due to conductivity modulation in the drift region
Data Source
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AI summary
The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.