Laterally Graded SiGe PFET Channel for Interface Trap Reduction
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Solution Overview
Problem
Conventional silicon-germanium channel regions in field-effect transistors are prone to strain relaxation and broken bonds at the interface with the buried oxide layer, leading to elevated interface trap density and reduced carrier mobility, affecting device performance.
Innovation Solution
A laterally graded Silicon-Germanium channel region is implemented, where the Germanium percentage is tuned along the width of the channel, with a lower percentage closest to the NFET region and a higher percentage farther away, using a thermal condensation process and lithography to form a high threshold voltage PFET device with improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional thermal condensation process is used to form silicon-germanium channel region, then device operation speed is improved, but strain relaxation and broken bonds occur at the interface with buried oxide layer
Solution Approach 1:
The patent applies local quality by implementing a laterally graded germanium concentration profile in the channel region, where the germanium percentage varies laterally from 0% at the NFET region interface to a maximum value (e.g., 20-30%) at the PFET channel center. This spatial variation in composition allows the interface region to maintain structural stability while the channel center provides high-speed carrier transport, thus resolving the contradiction between speed and interface reliability.
Solution Approach 2:
The patent changes the germanium concentration parameter laterally across the channel width, creating a gradient profile that transitions from low germanium content near the NFET interface to high germanium content at the channel center. This parameter change enables the interface region to have lower strain (improving reliability) while the channel center maintains high carrier mobility (improving speed), thereby resolving the technical contradiction.
2Reliability
If vertical gradient of germanium concentration is used in silicon-germanium channel region, then interface trap density is reduced, but device complexity increases
Solution Approach 1:
The patent transitions from a vertical gradient approach (previous art) to a lateral gradient approach, changing the dimension in which the germanium concentration varies. By implementing the gradient laterally across the channel width rather than vertically through the channel thickness, the patent simplifies the fabrication process while achieving the same benefit of reduced interface trap density. This dimensional change eliminates the need for complex multi-step epitaxial growth with vertical composition control.
3Speed
If laterally graded silicon-germanium channel region is implemented, then carrier mobility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies partial action by implementing the germanium gradient only in the lateral direction across the channel width, while maintaining a constant or simple vertical composition profile. This partial implementation of grading (only lateral, not vertical) achieves the desired carrier mobility improvement without requiring precise control of germanium concentration in both lateral and vertical dimensions simultaneously, thus reducing manufacturing precision requirements compared to full three-dimensional composition control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances Ion vs. Ioff performance, eliminates the need for a masking step in fabrication, and allows independent tuning of Vtsat, resulting in improved device performance and reduced strain relaxation.
Implementation Method 1
perform a thermal condensation process. Germanium is transported from the epitaxial silicon-germanium layer to the device layer and throughout the channel region down to the buried oxide layer.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a device with a laterally graded channel region and methods of manufacture. The structure includes a PFET region with a laterally graded semiconductor channel region under a gate material.