Lateral Traces in Cavity Walls for High-Density Interconnects
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Solution Overview
Problem
The challenge is to increase the density of interconnections between a substrate and an electrical component positioned in a cavity defined in the substrate, while reducing the number of layers needed for interconnection, thereby improving the performance of electronic devices.
Innovation Solution
Incorporating lateral traces that extend through the wall of the cavity, allowing for electrical communication pathways between the substrate and electrical components within the same layer, thereby increasing interconnection density and repurposing substrate portions for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional vertical interconnection methods are used, then electrical components can be connected to the substrate, but the interconnection density is limited and additional layers are required
Solution Approach 1:
The patent transitions from traditional vertical interconnection (z-dimension) to lateral interconnection through the cavity wall (x-y plane). The lateral trace extends horizontally through the cavity wall to contact the semiconductor die, enabling electrical connection without requiring additional vertical layers. This dimensional shift increases interconnection density within the same layer structure.
Solution Approach 2:
The lateral trace is nested within the cavity structure itself, utilizing the cavity wall as the transmission medium. The trace is formed within the dielectric material of the cavity wall, effectively nesting the interconnection path within the existing structural envelope rather than adding external layers.
2Reliability
If multiple layers are used for interconnection, then electrical pathways can be established, but device performance is reduced due to increased complexity and layer count
Solution Approach 1:
By moving the interconnection path to the lateral dimension through the cavity wall, the patent reduces the number of vertical layers required. This maintains reliable electrical connection while improving device performance by reducing signal path length and minimizing layer-induced parasitics.
3Quantity of substance
If lateral traces extending through cavity walls are implemented, then interconnection density increases and layer count is reduced, but manufacturing complexity may increase
Solution Approach 1:
The lateral trace is formed during the cavity formation process itself, before the semiconductor die is mounted. The dielectric material is deposited and patterned to create the lateral trace path, and then the cavity is etched away, leaving the trace embedded in the cavity wall. This preliminary formation simplifies subsequent assembly steps.
Solution Approach 2:
The patent merges the cavity formation process with the interconnection trace formation process. Both structures are created simultaneously through integrated fabrication steps, reducing the total number of manufacturing operations compared to forming vertical interconnections through separate layer deposition and via drilling.
Data Source
AI summary
An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.