Laterally Shifted Vertical Interconnections for 3D Memory Bonding
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Solution Overview
Problem
Current methods for stacking semiconductor dies lack efficient vertical interconnection solutions, limiting the density and performance of three-dimensional memory devices.
Innovation Solution
The implementation of laterally offset through-dielectric via structures and bonded assemblies that utilize a support die with peripheral circuitry to control memory stack structures, enabling vertical interconnection between memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias are used for vertical interconnection, then interconnection reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the via structures from the substrate and relocates them to the bonding pads on the memory die surface. This eliminates the need for expensive through-substrate vias while maintaining vertical interconnection functionality through laterally-offset vias that connect bonding pads to memory stack structures.
Solution Approach 2:
The patent introduces bonding pads as intermediary elements that mediate between the support die and memory stack structures. These bonding pads serve as connection points that enable vertical interconnection through laterally-offset vias, replacing the direct through-substrate via approach.
2Quantity of substance
If vertical interconnection density is increased, then memory device density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnection structure into distinct components: support die, bonding pads, laterally-offset vias, and memory stack structures. This segmentation allows each component to be optimized independently and simplifies the overall manufacturing process by breaking down the complex vertical interconnection into manageable stages.
Solution Approach 2:
The patent transitions from traditional vertical vias to laterally-offset vias, introducing a lateral dimension to the interconnection geometry. This dimensional change enables increased vertical interconnection density while maintaining manufacturability through standard via formation processes applied in a lateral offset configuration.
3Adaptability or versatility
If peripheral circuitry is integrated on support die, then memory die control functionality is improved, but bonding interface area increases
Solution Approach 1:
The patent applies local quality by concentrating peripheral circuitry specifically on the support die rather than distributing it across all dies. This localized integration provides the necessary control functionality while keeping the bonding interface area minimal, as only the essential bonding pads require alignment and connection.
Data Source
AI summary
A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.