Layered Bridge Interconnect Structure for Fine-Pitch IC Reliability
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Solution Overview
Problem
Current technologies face challenges in achieving a finer pitch for interconnect structures in integrated circuit assemblies, leading to yield failures and elevated electromigration risks due to limitations in solder bump height and copper diffusion, especially for smaller pitch areas.
Innovation Solution
The implementation of embedded bridge interconnections with layered interconnect structures, which include a bridge composed of glass or semiconductor material, a via structure with a first conductive material, a barrier layer with a second conductive material, and a solder layer with a third conductive material, to route electrical signals and mitigate electromigration risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a finer pitch is used for interconnect structures at the FLI level, then communication speed and performance are improved, but manufacturing precision and yield performance deteriorate due to limitations in solder bump height and volume
Solution Approach 1:
The patent transitions from a single-layer solder bump interconnect to a multi-layer stacked interconnect structure. The first conductive layer with via structures is stacked with a second conductive layer containing solder bumps, creating a three-dimensional interconnect architecture. This dimensional change allows the interconnect to achieve finer pitch at the FLI level while maintaining sufficient solder volume and height for reliable manufacturing, as the conductive pathways are distributed across multiple layers rather than confined to a single plane.
Solution Approach 2:
The patent employs composite interconnect structures combining different materials and configurations: copper via structures in the first conductive layer, solder bumps in the second conductive layer, and intermediate coupling structures. This composite approach allows each layer to optimize its function - the via structures provide precise electrical alignment at fine pitch, while the solder bumps provide robust mechanical and electrical connection, thereby improving both communication speed and manufacturing yield.
2Volume of moving object
If solder bump height and volume are limited, then assembly compactness is improved, but reliability deteriorates due to non-contact opens and bump cracks
Solution Approach 1:
By stacking conductive layers vertically, the patent increases the effective solder volume and height in the vertical dimension while maintaining a compact footprint in the horizontal plane. The first conductive layer with via structures is positioned below the second conductive layer with solder bumps, creating a distributed three-dimensional interconnect volume that enhances reliability without increasing overall assembly size.
Solution Approach 2:
The patent segments the interconnect function across multiple conductive layers and structural components. The via structures in the first layer handle electrical alignment and signal routing, while the solder bumps in the second layer provide mechanical bonding and electrical connection. This segmentation allows each component to be optimized independently - via structures can be precisely formed at fine pitch, while solder bumps can maintain adequate volume for reliability, thereby resolving the contradiction between compactness and reliability.
3Ease of manufacture
If copper diffusion is not prevented, then manufacturing simplicity is maintained, but electromigration risk increases
Solution Approach 1:
The patent introduces intermediate barrier layers and distinct conductive material layers between copper via structures and solder bumps. These intermediate layers act as diffusion barriers that prevent copper atoms from migrating into the solder and surrounding materials. The barrier layers are integrated into the multi-layer stack, adding minimal manufacturing complexity while effectively eliminating electromigration risks by blocking the diffusion pathway.
Solution Approach 2:
The patent uses composite interconnect structures with different conductive materials in different layers - copper in via structures, solder in bumps, and intermediate barrier materials. This material differentiation creates natural diffusion barriers at each material interface, preventing copper migration without requiring complex additional processing steps. The composite structure inherently provides electromigration protection while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances assembly performance, reduces yield loss, and improves reliability by inhibiting copper diffusion and providing a higher, more compliant first-level interconnect joint with increased standoff height.
Implementation Method 1
a barrier layer with a second conductive material, the barrier layer configured to inhibit diffusion
Implementation Method 2
a via structure with a first conductive material, the via structure being disposed to route the electrical signals
Data Source
AI summary
Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.