Layered Clock Architecture for Flexible Frequency Control
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Solution Overview
Problem
High-speed computing assemblies face challenges in flexible frequency adjustment and synchronization, leading to correctable and uncorrectable errors due to fixed frequency topology structures, limiting computing power and expansion.
Innovation Solution
A clock architecture with multiple clock module layers, each containing a local clock generator, selection switch circuit, and clock buffer circuits, allowing selection between local and external clock signals for flexible regulation and control, supported by a host server.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed frequency topology structure is used in high-speed computing assembly, then communication frequency synchronization is maintained, but the structure cannot be expanded and frequency cannot be flexibly adjusted
Solution Approach 1:
The patent implements dynamic frequency selection by equipping each clock module with a selection switch circuit that can dynamically switch between local clock signals and external clock signals based on enable signals. This dynamic configuration allows the system to adapt frequency topology structures without compromising synchronization reliability, resolving the contradiction between flexibility and reliability.
Solution Approach 2:
The patent segments the clock distribution system into independent clock modules, each with its own selection switch circuit. This segmentation allows individual modules to be independently configured and switched between different clock sources, enabling flexible frequency adjustment while maintaining overall system synchronization through coordinated control.
2Productivity
If a fixed frequency topology structure is used, then communication errors are reduced, but computing power and expansion capability are limited
Solution Approach 1:
The selection switch circuit serves multiple functions: it can switch between local and external clock signals, support different frequency topologies, and enable flexible configuration of clock modules. This multi-functionality allows a single circuit component to handle various computing power requirements and expansion scenarios without proportionally increasing system complexity.
Solution Approach 2:
The patent enables parameter changes in frequency topology by using the selection switch circuit to change clock signal sources and configurations. This allows the system to adjust frequency parameters dynamically to match different computing power levels and expansion needs while maintaining manageable complexity through standardized switching mechanisms.
3Adaptability or versatility
If phase deviation between communication frequencies is large, then frequency adjustment flexibility is improved, but communication errors occur
Solution Approach 1:
The enable signal mechanism provides feedback control for the selection switch circuit, allowing the system to monitor and respond to frequency synchronization conditions. This feedback enables the system to adapt frequency topologies while preventing phase deviations that would cause communication errors, balancing adaptability with error prevention.
Data Source
AI summary
A clock architecture, including one or more clock module layers; each clock module layer including one or more clock modules, each clock module including a local clock generator, a selection switch circuit and a plurality of clock buffer circuits; wherein the local clock generator is configured to generate an independent local clock signal; a first input terminal of the selection switch circuit receives the local clock signal, a second input terminal of the selection switch circuit receives an external clock signal, a plurality of output terminals of the selection switch circuit are respectively connected to input terminals of the plurality of clock buffer circuits, and an enable terminal of the selection switch circuit is configured to receive an enable signal; and the selection switch circuit is configured to enable, all the output terminals to output the local clock signal or enable all the output terminals to output the external clock signal, according to the enable signal.