Layered Silicon Film Doping for Recessed-Channel MOSFETs
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Solution Overview
Problem
The existing method for manufacturing semiconductor devices with recessed-channel MOSFETs in memory cell arrays and planar MOSFETs in peripheral circuits faces challenges in achieving sufficient impurity concentration near the bottom of the silicon electrode film, leading to depletion of gate electrodes and reduced operational speed due to insufficient ion implantation energy and conductivity type inversion issues.
Innovation Solution
A method involving the consecutive deposition of a doped silicon layer and a non-doped silicon layer over a silicon substrate, followed by specific ion implantation and heat treatment to form conductivity-type silicon films, ensuring sufficient impurity dosage and preventing impurity diffusion towards the channel, thereby maintaining adequate impurity concentration and operational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single ion implantation step is used for both recessed-channel MOSFETs and planar MOSFETs, then the manufacturing process throughput is improved, but the impurity concentration near the bottom of the silicon electrode film in recessed-channel MOSFETs becomes insufficient
Solution Approach 1:
The ion implantation process is divided into two separate steps: a first ion implantation step for planar MOSFETs and a second ion implantation step for recessed-channel MOSFETs. This segmentation allows each step to be optimized for its specific target, ensuring sufficient impurity concentration at the bottom of the silicon electrode film in recessed-channel MOSFETs while maintaining appropriate doping for planar MOSFETs, thereby resolving the contradiction between throughput and doping precision.
Solution Approach 2:
The first ion implantation step is performed as a preliminary action before the second ion implantation step. This preliminary doping establishes a base impurity concentration in the silicon electrode film, and the subsequent second implantation step adds additional impurities specifically to reach the bottom regions of recessed-channel MOSFETs, ensuring adequate total impurity concentration where needed.
2Speed
If the acceleration energy of ion implantation is reduced for thinner silicon electrode films in peripheral circuits, then the operational speed is improved, but the impurity diffusion depth is insufficient for thicker films in memory cell arrays
Solution Approach 1:
Different acceleration energies are applied locally to different regions: a first acceleration energy is used for implanting into planar MOSFETs with thinner silicon electrode films in peripheral circuits, while a second, higher acceleration energy is used for implanting into recessed-channel MOSFETs with thicker silicon electrode films in memory cell arrays. This local differentiation allows each region to receive the appropriate energy for its specific thickness, resolving the contradiction between speed and diffusion depth.
3Manufacturing precision
If in-situ doping is used during silicon electrode film deposition, then the impurity concentration is improved, but conductivity type inversion occurs in peripheral circuit regions
Solution Approach 1:
The in-situ doping step is extracted or removed from the deposition process. Instead of incorporating dopants during silicon electrode film deposition, the patent performs separate post-deposition ion implantation steps. This eliminates the risk of conductivity type inversion in peripheral circuit regions while still achieving sufficient impurity concentration through the controlled implantation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the ON-current of MOSFETs by preventing depletion and maintaining optimal impurity distribution, improving data retention and operational speed in DRAM devices by ensuring sufficient impurity concentration and stable threshold voltage.
Implementation Method 1
consecutively depositing a doped silicon layer doped with a first-conductivity-type dopant and a non-doped silicon layer to form a layered silicon film
Implementation Method 2
implanting a first-conductivity-type dopant into a portion of the layered silicon film in the first region; implanting a second-conductivity-type dopant into a portion of the layered silicon film in the second region
Implementation Method 3
A heat treatment is then conducted to diffuse the dopant within the gate electrodes for activation of the dopant
Implementation Method 4
heat treating the layered silicon film to form a first-conductivity-type silicon film in the first region and a second-conductivity-type silicon film in the second region
Data Source
AI summary
A method for manufacturing a semiconductor device includes the step of depositing a doped silicon layer doped with a first-conductivity-type dopant and a non-doped silicon layer to form a layered silicon film, implanting a first-conductivity-type dopant into a portion of the layered silicon film disposed in a first region, implanting a second-conductivity-type dopant into a portion of the layered silicon film disposed in a second region, and heat treating the layered silicon film to form a first-conductivity-type silicon film in the first region and a second-conductivity-type silicon film in the second region.