Selective Layout Data Extraction for Electron Beam Write Error Verification
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Solution Overview
Problem
In electron beam writing apparatuses, verifying write errors in layouts with multiple chip arrangements leads to unnecessary verification time, as existing methods create verification data for regions that do not require verification, especially when the same chip is arranged at multiple portions, resulting in wasted time and inefficiency.
Innovation Solution
A method and apparatus for selectively extracting and deleting unnecessary data from layout data to create verification data only for the specific portion causing the write error, using a data selection unit, extraction unit, and verification data creation unit to reduce examination time by focusing on the relevant data for error reproduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification data is created for all portions of the target object when the same chip is arranged at multiple portions, then complete verification coverage is achieved, but verification time is wasted on portions that do not require verification
Solution Approach 1:
The patent extracts only the necessary layout data corresponding to the error-causing function from the complete layout data. When the same chip is arranged at multiple portions, the system identifies and extracts data only for the specific portion that caused the error, excluding data for other portions. This extraction principle resolves the contradiction by maintaining verification reliability for the error-causing portion while eliminating unnecessary verification time for other portions.
Solution Approach 2:
The patent segments the layout data into multiple portions corresponding to different chip arrangements. By dividing the complete layout data into separate portions and selectively processing only the relevant segment (the one causing the error), the system achieves both complete verification coverage for necessary portions and reduced verification time by excluding unnecessary portions from processing.
2Reliability
If all layout data is processed for error verification, then no verification errors are missed, but processing efficiency decreases due to unnecessary data handling
Solution Approach 1:
The patent applies the extraction principle by removing unnecessary layout data from the verification process. Instead of processing all layout data, the system extracts only the specific portion corresponding to the error-causing function. This ensures that error detection completeness is maintained for the relevant portion while significantly improving verification efficiency by eliminating processing of unnecessary data.
Solution Approach 2:
The patent applies local quality by treating different portions of the layout data differently based on their relevance to the error. The error-causing portion receives full verification processing to ensure detection completeness, while other portions are excluded from processing to improve efficiency. This differentiated approach resolves the contradiction between reliability and productivity.
3Reliability
If verification data includes all chip arrangements, then comprehensive testing is performed, but data transfer time and information leakage risks increase
Solution Approach 1:
The patent extracts only the necessary layout data for the error-causing portion from the complete layout data before transferring to the verification apparatus. This extraction reduces data transfer time by eliminating unnecessary data while maintaining testing comprehensiveness for the relevant error-causing portion. It also reduces information leakage risks by minimizing the amount of sensitive layout data that needs to be transferred.
Data Source
AI summary
A write error verification method of a writing apparatus verifying a write error after a write operation being started in the writing apparatus to which layout data containing a figure pattern to be formed is input and which forms the figure pattern on a target object based on the layout data input, the write error verification method includes: if a write error occurs in a process between input of the layout data into the writing apparatus and inspection of the target object on which the figure pattern is formed, selecting a part of the layout data necessary for operation of a function that has caused the write error; extracting parts of the layout data corresponding to a selected part of the layout data for all of a plurality of portions of the target object if a pattern indicated by the selected part of the layout data is arranged at the plurality of portions of the target object; creating verification data by deleting at least one parts extracted for at least one portions other than a portion that has caused the write error from extracted parts of the layout data and by using remaining data; and reproducing the operation of the function that has caused the write error using the verification data to output a result of the reproducing.