Semiconductor Layout Modification for Critical Dimension Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing exposure techniques for semiconductor manufacturing processes face challenges in uniformly assessing exposure issues, particularly at advanced technology nodes, leading to non-uniformity in critical dimensions during the fabrication of integrated circuits.
Innovation Solution
A layout modification method is introduced, which involves calculating the uniformity of critical dimensions in patterned layers and using compensation indices to adjust the layout, specifically employing the Mask Error Enhancement Factor (MEEF) and compensation amounts to generate a modified layout that compensates for non-uniformity caused by light leakage and reflection, without requiring additional thin films to absorb light.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing exposure techniques are used for advanced technology nodes, then production efficiency is maintained, but uniformity of critical dimensions deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating compensation amounts and generating a modified layout before the actual exposure process. The system computes the Mask Error Enhancement Factor (MEEF) and determines compensation values for different regions in advance, then applies these corrections to the layout data prior to manufacturing. This preliminary computation and correction step ensures that when exposure occurs, the critical dimension uniformity is already optimized, eliminating the need for post-processing adjustments while maintaining production efficiency.
2Manufacturing precision
If additional thin films are added to absorb light leakage, then uniformity of critical dimensions improves, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the layout parameters (dimensions, positions, shapes of patterns) rather than changing the physical process parameters or adding materials. The system calculates compensation amounts based on MEEF analysis and applies these as parameter adjustments to the layout data. This digital/parametric approach corrects exposure non-uniformity through mathematical compensation of pattern dimensions and positions, avoiding the need to add physical thin films or modify the exposure process itself, thereby maintaining process simplicity while improving critical dimension uniformity.
Data Source
AI summary
A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.