Layout Optimizer for IC Design Data Reduction
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Solution Overview
Problem
Current methods for verifying if features of a target integrated circuit layout will print correctly on a wafer are inefficient, especially as IC dimensions shrink, due to massive computation requirements and the inability to guarantee detection of all errors, even with advanced design for manufacturing techniques.
Innovation Solution
The method involves reducing the data volume of the target layout by removing features that have already been analyzed and determined to print correctly, fragmenting remaining features into edge fragments, and applying optical and process correction tools to analyze sensitivity to process variations, thereby creating a revised layout that can be analyzed more efficiently with design for manufacturing tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full model-based treatment is used to analyze all features in the target layout, then the reliability of detecting manufacturing problems is improved, but the computation time and complexity increase massively
Solution Approach 1:
The patent segments the target layout into multiple regions and divides the computation into sequential passes. Each pass analyzes a subset of features rather than the entire layout simultaneously, reducing the computational burden while maintaining detection reliability through multiple targeted analyses.
Solution Approach 2:
The patent performs preliminary analysis to identify and remove features that are guaranteed to print correctly before conducting the full rigorous analysis. This preliminary filtering step eliminates unnecessary computations on features that will not cause manufacturing problems, significantly reducing computation time while preserving detection reliability for problematic features.
2Productivity
If the data volume of the target layout is reduced by removing features, then the computation time is reduced, but the detection capability may be compromised
Solution Approach 1:
The patent applies preliminary analysis using simplified criteria to identify and remove only those features that are guaranteed to print correctly. This preliminary filtering preserves all potentially problematic features for subsequent rigorous analysis, maintaining detection capability while reducing data volume and computation time.
Solution Approach 2:
The patent introduces an intermediary filtering step that acts as a mediator between the full layout and the rigorous analysis. This intermediary layer uses efficient preliminary checks to eliminate safe features while preserving suspicious ones, enabling both fast processing and reliable detection without compromising either objective.
3Productivity
If a library of known defective patterns is used for analysis, then the analysis speed is improved, but the ability to detect new or unknown errors is lost
Solution Approach 1:
The patent segments the analysis into two distinct phases: a fast library-based filtering phase that quickly eliminates known good patterns, and a rigorous model-based analysis phase that detects both known and unknown defects. This segmentation allows the system to benefit from both the speed of library matching and the comprehensive detection capability of full analysis.
Solution Approach 2:
The patent performs preliminary filtering using the library of known defective patterns to quickly eliminate obvious cases. Features that match known defective patterns are flagged for further analysis, while those that clearly match known good patterns are excluded. This preliminary action maintains speed while preserving the ability to detect new errors through subsequent rigorous analysis of remaining features.
Data Source
AI summary
A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.