LC Tank Phase Detector Clocking for Static Sampling Phase Adjust
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Solution Overview
Problem
Existing phase-locked loop (PLL) arrangements in data recovery circuits face challenges in achieving optimal phase alignment due to suboptimal sampling phases, leading to increased jitter and bit errors, particularly in fiber optic communication channels, where static phase adjust features require additional power and can result in incorrect phase adjustments.
Innovation Solution
A binary phase detector utilizing two LC tank clock drivers with individually adjustable center frequencies and a programmable delay between their outputs to determine the data sampling phase, allowing for precise static phase adjustments without the need for an auxiliary channel, thereby improving phase alignment and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an auxiliary flip-flop with a phase shifted clock is used to implement static phase adjust, then the significant instance in time can be moved within a data eye, but additional power is consumed and bit errors can lead to incorrect phase adjustments
Solution Approach 1:
The patent makes the existing clock drivers perform multiple functions: they both generate clock signals and provide static phase adjustment capability through programmable delay elements integrated into the clock driver circuitry, eliminating the need for separate auxiliary phase adjustment circuits
Solution Approach 2:
The patent combines the phase adjustment function with the clock driver function by integrating programmable delay elements directly into the clock driver circuit, merging what were previously separate functions into a unified structure that reduces power consumption
2Ease of operation
If an auxiliary flip-flop with a phase shifted clock is used to implement static phase adjust, then the significant instance in time can be moved within a data eye, but bit errors can lead to incorrect phase adjustments that increase jitter
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector monitors the alignment between clock edges and data transitions, and uses this information to automatically adjust the programmable delay settings, ensuring that phase adjustments are corrected if bit errors occur and preventing jitter increase
3Device complexity
If fixed center frequencies are used in LC tanks, then the circuit design is simpler, but the data sampling phase cannot be precisely adjusted
Solution Approach 1:
The patent transforms the static center frequency of LC tanks into a dynamic, programmable parameter by introducing control circuits that can adjust the center frequency based on desired phase adjustment requirements, allowing precise phase control while maintaining relatively simple hardware architecture
Solution Approach 2:
The patent changes the center frequency parameter of the LC tanks from fixed to programmable values, enabling precise control of the data sampling phase by adjusting the frequency parameter in response to phase alignment requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes bit errors and jitter by allowing for precise control of the data sampling phase, enhancing the immunity to data transitions and optimizing power consumption by using LC tank clock drivers with adjustable center frequencies.
Implementation Method 1
two LC resonant tanks as clock drivers, where the two LC tanks have individually adjustable center frequencies
Data Source
AI summary
A phase detector includes a first clock driver comprising a first LC tank. The first clock driver provides a strobe to a plurality of flip-flops associated with sampled data being received by the phase detector. The second clock driver includes a second LC tank. The second clock driver provides a strobe to a plurality of flip-flops associated with sampling the phase error of the phase detector. The first and second LC tanks have different adjustable center frequencies and experience a programmable delay between the outputs of the first and second clock drivers so as to determine the data sampling phase of the phase detector.