LCD Array Substrate Layout for Higher Aperture Ratio
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Solution Overview
Problem
The 3T-plus pixel architecture in current liquid crystal display technologies suffers from a reduced aperture ratio of pixel electrodes due to the second array common electrode crossing the display area, which reduces transmittance.
Innovation Solution
The array substrate design includes a shared common electrode and a gate scanning line on the same layer, with a first via exposing part of the shared common electrode and the drain electrode of a third thin film transistor, allowing electrical connection through a conductive film layer, ensuring the shared common electrode only exists in a non-display area between primary and sub-pixel electrodes, thus avoiding reduction in aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second array common electrode is disposed to cross the display area vertically to share voltage with sub pixel electrode, then the crosstalk problem is solved, but the aperture ratio of pixel electrodes is reduced
Solution Approach 1:
The shared common electrode is repositioned from a vertical arrangement crossing the display area to a horizontal arrangement along the gate scanning line direction. This dimensional change allows the electrode to maintain its voltage sharing function while being confined to the non-display area, thus preventing aperture ratio reduction.
Solution Approach 2:
The shared common electrode is extracted from the display area and relocated to the non-display area where the gate scanning line is positioned. This separation removes the conflicting element from the active display region, preserving both crosstalk suppression capability and aperture ratio.
2Area of stationary object
If the shared common electrode is disposed on the same layer as gate scanning line in non-display area, then the aperture ratio is improved, but the electrical connection complexity increases
Solution Approach 1:
The shared common electrode is merged with the gate scanning line layer structure, both being disposed on the same layer in the non-display area. This integration simplifies the overall device architecture by reducing the number of layers and eliminating the need for additional via structures to reach the shared common electrode.
Data Source
AI summary
An array substrate and a liquid crystal display panel are disclosed. In the array substrate, a shared common electrode and a gate scanning line are disposed on a same layer, and a drain electrode of a third thin film transistor is electrically connected to the shared common electrode by a conductive film layer. Therefore, the shared common electrode only exists in a non-display area between a primary pixel electrode and a sub pixel electrode and does not need to pass the primary pixel electrode and the sub pixel electrode, thereby improving an aperture ratio of pixel electrodes and transmittances.