LCD Array Substrate Common Electrode Layout for Light Leakage Reduction
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Solution Overview
Problem
Large-size LCDs face defects such as horizontal and vertical lines due to a relatively large overlapped area between the common electrode and the black matrix, leading to excessive coupling capacitance and light leakage in the startup L0 state.
Innovation Solution
The array substrate design includes a common electrode connected to adjacent sub-pixels through a common connection portion, with a specific overlapped region between the common connection portion and the gate line, reducing the overlapped area between the common electrode and the black matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the common electrode is connected to adjacent sub-pixels through a common connection portion with a specific overlapped region design, then the coupling capacitance between the common electrode and the black matrix is reduced, but the structural complexity of the common connection portion increases
Solution Approach 1:
The common connection portion is divided into multiple segments with different overlapped regions relative to the gate line. By segmenting the connection structure, the patent reduces the total overlapped area between the common electrode and the black matrix, thereby reducing coupling capacitance while maintaining electrical connectivity across sub-pixels.
Solution Approach 2:
Different portions of the common connection portion have different overlapped regions with the gate line (first overlapped region with first width, second overlapped region with second width). This local variation in geometry optimizes the balance between electrical connection and capacitance reduction, applying different structural characteristics to different locations based on functional requirements.
2Object-affected harmful factors
If the overlapped area between the common electrode and the black matrix is reduced through the common connection portion design, then light leakage and display defects are minimized, but the manufacturing precision requirements increase
Solution Approach 1:
The common connection portion is designed in advance with predetermined first and second overlapped regions relative to the gate line. This preliminary design establishes the geometric parameters before manufacturing, guiding the fabrication process to achieve the desired overlapped area reduction and minimize light leakage while providing clear manufacturing targets.
Solution Approach 2:
The patent modifies the geometric parameters of the common connection portion, specifically the widths of the first and second overlapped regions. By changing these dimensional parameters, the design achieves reduced overlapped area between the common electrode and black matrix, thereby reducing light leakage and display defects like horizontal and vertical lines.
3Productivity
If the common connection portion has a specific overlapped region design with controlled widths, then process yield is improved, but the device complexity increases
Solution Approach 1:
The common connection portion features an asymmetric design where the first overlapped region has a first width and the second overlapped region has a second width, which are deliberately different. This asymmetric configuration optimizes the balance between electrical performance and manufacturing yield by creating a structure that is more tolerant to process variations while maintaining functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the coupling capacitance between the common electrode and the black matrix, minimizing light leakage and defects like horizontal and vertical lines in the startup L0 state, while maintaining improved process yield.
Implementation Method 1
Large-size LCDs face defects such as horizontal and vertical lines due to a relatively large overlapped area between the common electrode and the black matrix, leading to excessive coupling capacitance
Implementation Method 2
By controlling a common electrode and a pixel electrode, an electric field is formed to drive the liquid crystal to deflect, thereby implementing gray scale display
Implementation Method 3
drive the liquid crystal to deflect, thereby implementing gray scale display
Data Source
AI summary
The present disclosure provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate includes a plurality of gate lines (20) and a plurality of data lines (50) disposed on a base substrate (11), the plurality of gate lines (20) extend along a first direction, the plurality of data lines (50) extend in a second direction, the plurality of gate lines (20) and the plurality of data lines (50) are intersected to define a plurality of sub-pixels, the sub-pixel includes a thin film transistor (10), a pixel electrode (80) and a common electrode (90), the common electrode (90) in one sub-pixel is connected with the common electrode (90) in the adjacent sub-pixel through a common connection portion (110).